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PDF IDT72V36100 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V36100 | |
| Descripción | 3.3 VOLT HIGH-DENSITY SUPERSYNC II 36-BIT FIFO | |
| Fabricantes | Integrated Device Tech | |
| Logotipo |  |
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3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO
1,024 x 36, 2,048 x 36
IDT72V3640, IDT72V3650
4,096 x 36, 8,192 x 36
IDT72V3660, IDT72V3670
16,384 x 36, 32,768 x 36
IDT72V3680, IDT72V3690
65,536 x36, 131,072 x 36
IDT72V36100, IDT72V36110
FEATURES:
• Choose among the following memory organizations:Commercial
IDT72V3640 1,024 x 36
IDT72V3650 2,048 x 36
IDT72V3660 4,096 x 36
IDT72V3670 8,192 x 36
IDT72V3680 16,384 x 36
IDT72V3690 32,768 x 36
IDT72V36100 65,536 x 36
IDT72V36110 131,072 x 36
• 133 MHz operation (7.5 ns read/write cycle time)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in the 128-pin Thin Quad Flat Pack (TQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK
D0 -Dn (x36, x18 or x9)
LD SEN
WRITE CONTROL
LOGIC
BE
IP
BM
IW
OW
MRS
PRS
WRITE POINTER
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
INPUT REGISTER
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
OE Q0 -Qn (x36, x18 or x9)
4667 drw 01
The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
© 2001 Integrated Device Technology, Inc.
1
APRIL 2001
DSC-4667/3
1 page  
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–D35 Data Inputs
MRS MasterReset
I Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
I MRS initializes the read and write pointers to zero and sets the output register to all zeroes.DuringMasterReset,the
FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat, zero
latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
PRS PartialReset
I PRS initializes the read and write pointers to zero and sets the output register to all zeroes.DuringPartialReset,the
existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained.
RT Retransmit
I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.
FWFT/SI First Word Fall
I During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
Through/Serial In
functions as a serial input for loading offset registers.
OW(1)
OutputWidth
I This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
IW(1) InputWidth
I This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration.
BM(1) Bus-Matching
I BMworks with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration.
BE(1) Big-Endian/
Little-Endian
I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
will select Little-Endian format.
RM(1) RetransmitTiming I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode
normal latency mode.
PFM(1) Programmable
Flag Mode
I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
will select Synchronous Programmable flag timing mode.
IP(1) Interspersed Parity I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity
mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect
the data written to and read from the FIFO.
FSEL0(1) Flag Select Bit 0
I DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesfortheprogrammable
flags PAE and PAF. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1
I DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesfortheprogrammable
flags PAE and PAF. There are up to eight possible settings available.
WCLK WriteClock
I WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheFIFOandoffsetsinto theprogrammableregisters
for parallel programming, and when enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN WriteEnable
I WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK Read Clock
I WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheFIFO memoryandoffsetsfromtheprogrammable
registers.
REN Read Enable
I REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
Output Enable
I OE controls the output impedance of Qn.
SEN Serial Enable
I SEN enables serial loading of programmable flag offsets.
LD Load
I This is a dual purpose pin. During Master Reset, the state of theLD input along with FSEL0 and FSEL1, determines
one of eight default offset values for thePAE and PAF flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.
FF/IR Full Flag/
O In the IDT Standard mode, the FF function is selected. FF indicates whether or Input Ready not theFIFOmemory
is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing
to the FIFO memory.
EF/OR Empty Flag/
Output Ready
O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-Full Flag
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-Empty Flag
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
HF
Half-Full Flag
O HF indicates whether the FIFO memory is more or less than half-full.
Q0–Q35 DataOutputs
O Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
state. Outputs are not 5V tolerant regardless of the state of OE.
NOTE:
1. Inputs should not change state after Master Reset.
5
5 Page 
TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE
Number of
Words in
FIFO
IDT72V3640
0
1 to n (1)
(n+1) to 512
513 to (1,024-(m+1))
(1024-m) to 1,023
1,024
IDT72V3650
0
1 to n (1)
(n+1) to 1,024
1,025 to (2048-(m+1))
(2048-m) to 2,047
2,048
IDT72V3660
0
1 to n (1)
(n+1) to 2,048
2,049 to (4,096-(m+1))
(4,096-m) to 4,095
4,096
IDT72V3670
0
1 to n (1)
(n+1) to 4,096
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
FF PAF HF PAE EF
H HHL
H HHL
HHHH
L
H
H
H HL H H
HL L H H
LLL H H
IDT72V3680
Number of
Words in
FIFO
0
1 to n(1)
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
NOTE:
1. See table 2 for values for n, m.
IDT72V3690
0
1 to n (1)
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
IDT72V36100
0
1 to n(1)
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
IDT72V36110
0
1 to n (1)
(n+1) to 65,536
65,537 to (131,072-(m+1))
(131,072-m) to 131,071
131,072
FF PAF HF PAE EF
H HHL L
H HHL H
H HHH H
H HLH H
H LLH H
L LLH H
TABLE 4 STATUS FLAGS FOR FWFT MODE
Number of
Words in
FIFO
IDT72V3640
0
1 to n+1
(n+2) to 513
514 to (1,025-(m+1))
(1,025-m) to 1,024
1,025
IDT72V3650
0
1 to n+1
(n+2) to 1,025
1,026 to (2,049-(m+1))
(2,049-m) to 2,048
2,049
IDT72V3660
0
1 to n+1
(n+2) to 2,049
2,050 to (4,097-(m+1))
(4,097-m) to 4,096
4,097
IDT72V3670
0
1 to n+1
(n+2) to 4,097
4,098 to (8,193-(m+1))
(8,193-m) to 8,192
8,193
IR PAF HF PAE OR
L HHL
H
L HHL
L
L HHH L
L HL H L
LLLH L
HL L H L
IDT72V3680
Number of
Words in
FIFO
0
1 to n+1
(n+2) to 8,193
8,194 to (16,385-(m+1))
(16,385-m) to 16,384
16,385
NOTE:
1. See table 2 for values for n, m.
IDT72V3690
0
1 to n+1
(n+2) to 16,385
16,386 to (32,769-(m+1))
(32,769-m) to 32,768
32,769
IDT72V36100
0
1 to n+1
(n+2) to 32,769
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
IDT72V36110
0
1 to n+1
(n+2) to 65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
IR PAF HF PAE OR
L HHL
H
L HHL
L
L HHH L
L HL H L
LLLH L
HL L H L
4667 drw 05
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT72V36100.PDF ] | |
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