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PDF 55N03LTA Data sheet ( Hoja de datos )
| Número de pieza | 55N03LTA | |
| Descripción | Logic Level FET | |
| Fabricantes | Philips | |
| Logotipo |  |
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 1. Logic Level FET - Philips  Hay una vista previa y un enlace de descarga de 55N03LTA (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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PHP/PHB/PHD55N03LTA
TrenchMOS™ Logic Level FET
Rev. 04 — 4 September 2002
Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP55N03LTA in a SOT78 (TO-220AB)
PHB55N03LTA in a SOT404 (D2-PAK)
PHD55N03LTA in a SOT428 (D-PAK).
2. Features
s Low on-state resistance
s Fast switching.
3. Applications
s Computer motherboard high frequency DC to DC converters.
4. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT428 simplified outlines and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
[1]
mb
mb
3 source (s)
mb mounting base,
connected to drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
2
1
Top view
3
MBK091
SOT428 (D-PAK)
Symbol
g
MBB076
d
s
[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
1 page  
Philips Semiconductors
PHP/PHB/PHD55N03LTA
TrenchMOS™ Logic Level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th) gate-source threshold voltage
IDSS drain-source leakage current
IGSS
RDSon
gate-source leakage current
drain-source on-state resistance
Dynamic characteristics
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 25 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±5 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 10 V; ID = 25 A
Tj = 25 °C
gfs forward transconductance
Qg(tot) total gate charge
Qgs gate-source charge
Qgd gate-drain (Miller) charge
Ciss input capacitance
Coss output capacitance
Crss reverse transfer capacitance
td(on)
turn-on delay time
tr rise time
td(off)
turn-off delay time
tf fall time
Source-drain diode
VDS = 25 V; ID = 25 A
ID = 55 A; VDD = 15 V; VGS = 5 V; Figure 13
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11
VDD = 15 V; ID = 55 A; VGS = 10 V; RG = 5 Ω
VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
IS = 55 A; VGS = 0 V
Min Typ Max Unit
25 - - V
22 - - V
1 1.5 2 V
0.5 - - V
- - 2.3 V
- 0.05 10 µA
- - 500 µA
- 10 100 nA
- 15 18 mΩ
- 25.5 30.6 mΩ
- 11 14 mΩ
- 32 - S
- 20 - nC
- 8 - nC
- 7 - nC
- 950 - pF
- 340 - pF
- 230 - pF
- 8 15 ns
- 45 80 ns
- 45 80 ns
- 40 60 ns
- 0.95 1.2 V
- 1.2 - V
9397 750 10143
Product data
Rev. 04 — 4 September 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5 of 14
5 Page 
Philips Semiconductors
PHP/PHB/PHD55N03LTA
TrenchMOS™ Logic Level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
EA
A2
b2 A1
mounting
base
D
HE
L2
2
1
L
3
b1
e
b wM A
e1
L1
c
D1
E1
0 10 20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1(1) A2 b
b1 b2
c
mm 2.38 0.65 0.93 0.89 1.1 5.46 0.4
2.22 0.45 0.73 0.71 0.9 5.26 0.2
D
6.22
5.98
D1 E
min.
4.0 6.73
6.47
E1 e e1 HE L
4.81 2.285 4.57 10.4 2.95
4.45 9.6 2.55
L1
min.
0.5
L2
0.9
0.5
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT428
TO-252
SC-63
w
y
max.
0.2 0.2
ISSUE DATE
99-09-13
01-12-11
Fig 16. SOT428 (D-PAK)
9397 750 10143
Product data
Rev. 04 — 4 September 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
11 of 14
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 55N03LTA.PDF ] | |
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