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PDF PCM1737 Data sheet ( Hoja de datos )
| Número de pieza | PCM1737 | |
| Descripción | 24-Bit/ 192kHz Sampling Enhanced Multi-Level/ Delta-Sigma/ Audio DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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®
PCM1737
PCM1737
For most current data sheet and other product
information, visit www.burr-brown.com
TM 24-Bit, 192kHz Sampling
Enhanced Multi-Level, Delta-Sigma, Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 24-BIT RESOLUTION
q ANALOG PERFORMANCE (VCC = +5V):
Dynamic Range: 106dB typ
SNR: 106dB typ
THD+N: 0.0015% typ
Full-Scale Output: 3.1Vp-p typ
q 4x/8x OVERSAMPLING DIGITAL FILTER:
Passband: 0.454fS
Stopband: 0.546fS
Stopband Attenuation: –82dB
Passband Ripple: ±0.002dB
q SAMPLING FREQUENCY: 10kHz to 192kHz
q SYSTEM CLOCK: 128, 192, 256, 384, 512, or
768fS with Auto Detect
q ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO DATA
q DATA FORMATS: Standard, I2S, and Left-Justified
q USER-PROGRAMMABLE MODE CONTROLS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
Soft Mute
Variable Oversampling for ∆Σ DACs
Zero Detect Mute
Zero Flags for Each Output
q DUAL SUPPLY OPERATION:
+5V Analog, +3.3V Digital
q 5V TOLERANT DIGITAL INPUTS
q SMALL SSOP-28 PACKAGE
APPLICATIONS
q A/V RECEIVERS
q DVD MOVIE AND AUDIO PLAYERS
q DVD ADD-ON CARDS FOR HIGH-END PCs
q HDTV RECEIVERS
q CAR AUDIO SYSTEMS
q OTHER APPLICATIONS REQUIRING 24-BIT
AUDIO
DESCRIPTION
The PCM1737 is a CMOS, monolithic, integrated
circuit which includes stereo digital-to-analog con-
verters and support circuitry in a small SSOP-28
package. The data converters utilize Burr-Brown’s
enhanced multi-level delta-sigma architecture, which
employs 4th-order noise shaping and 8-level ampli-
tude quantization to achieve excellent dynamic per-
formance and improved tolerance to clock jitter.
The PCM1737 accepts industry standard audio data
formats with 16- to 24-bit data, providing easy
interfacing to audio DSP and decoder chips. Sam-
pling rates up to 192kHz are supported. A full set
of user-programmable functions are accessible through
a 4-wire serial control port which supports register
write and read back functions.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1552C
Printed in U.S.A. March, 2000
1 page  
TYPICAL PERFORMANCE CURVES
All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
FREQUENCY RESPONSE
(Sharp Roll-Off)
0
0.003
PASSBAND RIPPLE
(Sharp Roll-Off)
–20 0.002
–40
0.001
–60
–80 0
–100
–120
–140
–160
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (x fS)
–0.001
–0.002
–0.003
0
0.1 0.2
0.3
Frequency (x fS)
0.4
0.5
0
–20
–40
–60
–80
–100
–120
–140
0
FREQUENCY RESPONSE
(Slow Roll-Off 1)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Frequency (x fS)
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0
TRANSITION CHARACTERISTICS
(Slow Roll-Off 1)
0.1 0.2 0.3 0.4 0.5 0.6
Frequency (x fS)
0
–20
–40
–60
–80
–100
–120
–140
0
FREQUENCY RESPONSE
(Slow Roll-Off 2)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Frequency (x fS)
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0
TRANSITION CHARACTERISTICS
(Slow Roll-Off 2)
0.1 0.2 0.3 0.4 0.5 0.6
Frequency (x fS)
®
5 PCM1737
5 Page 
REGISTER WRITE OPERATION
All Write operations for the serial control port use 16-bit
data words. Figure 6 shows the control data word format.
The most significant bit is the Read/Write (R/W) bit. When
set to ‘0’, this bit indicates a Write operation. There are
seven bits, labeled IDX[6:0], that set the register index (or
address) for the Write operation. The least significant eight
bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
Figure 7 shows the functional timing diagram for writing the
serial control port. ML is held at a logic ‘1’ state until a
register needs to be written. To start the register write cycle,
ML is set to logic ‘0’. Sixteen clocks are then provided on
MC, corresponding to the 16 bits of the control data word on
MDI. After the sixteenth clock cycle has completed, ML is
set to logic ‘1’ to latch the data into the indexed mode control
register.
SINGLE REGISTER READ OPERATION
Read operations utilize the 16-bit control word format shown
in Figure 6. For Read operations, the Read/Write (R/W) bit
is set to ‘1’. Read operations ignore the index bits, IDX[6:0],
of the control data word. Instead, the REG[6:0] bits in
Control Register 21 are used to set the index of the register
that is to be read during the Read operation. Bits IDX[6:0]
should be set to 00H for Read operations.
LRCK
BCK
DATA1-DATA3
tBCH
tBCL
tBCY
tBL
tLB
tDS tDH
SYMBOL
PARAMETER
MIN MAX
tBCY BCK Pulse Cycle Time
48 or 64fS(1)
tBCH
BCK High Level Time
35
tBCL
BCK Low Level Time
35
tBL
BCK Rising Edge to LRCK Edge
10
tLB
LRCK Falling Edge to BCK Rising Edge
10
tDS
DIN Set Up Time
10
tDH
DIN Hold Time
10
NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
UNITS
ns
ns
ns
ns
ns
ns
50% of VDD
50% of VDD
50% of VDD
FIGURE 5. Audio Interface Timing.
MSB
LSB
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D5 D4 D3 D2 D1 D0
Register Index (or Address)
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
Register Data
FIGURE 6. Control Data Word Format for MDI.
ML
MC
MDI X 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X D15 D14
FIGURE 7. Write Operation Timing.
11
PCM1737
®
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet PCM1737.PDF ] | |
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