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PDF PCM1727 Data sheet ( Hoja de datos )
| Número de pieza | PCM1727 | |
| Descripción | Stereo Audio DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE DUAL PLL TM | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® 49%
PCM1F7P27OE
PCM1727
TM Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
WITH PROGRAMMABLE DUAL PLL
FEATURES
q ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA
q COMPLETE STEREO DAC: Includes Digital
Filter and Output Amp
q DYNAMIC RANGE: 92dB
q MULTIPLE SAMPLING FREQUENCIES:
fS = 44.1kHz, 48kHz, 96kHz
q PROGRAMMABLE DUAL PLL CIRCUIT:
27MHz Master Clock Input
q GENERATED SYSTEM CLOCK
SCKO1: 33.8688MHz
SCK02: 384fS
SCK03: 768fS (44.1k/48kHz)
384fS (96kHz)
q NORMAL OR I2S DATA INPUT FORMATS
q SELECTABLE FUNCTIONS:
Soft Mute, Analog Output Mode
Digital Attenuator (256 Steps)
Digital De-emphasis
q +5V SINGLE POWER SUPPLY
DESCRIPTION
The PCM1727 is a complete low cost stereo audio
digital-to-analog converter (DAC) with a dual phase-
locked loop (PLL) circuit included. PLL-1 derives a
fixed 33.8688MHz (768fS, fS = 44.1kHz) system
clock (SCKO-1), and PLL-2 derives both the 384fS (fS
= 44.1k/48k/96kHz) system clock (SCKO-2), and the
768fS (fS = 44.1k/48kHz)/384fS (fS = 96kHz) system
clock (SCKO-3) from an external 27MHz reference
frequency. The DAC contains a 3rd-order ∆Σ modula-
tor, a digital interpolation filter, and an analog output
amplifier. The PCM1727 can accept 16-, 20-, or 24-bit
input data in either normal or I2S formats.
The digital filter performs an 8X interpolation func-
tion and includes selectable features such as soft mute,
digital attenuation and digital de-emphasis.
The PCM1727 is ideal for applications which combine
compressed audio and video data such as DVD, DVD
Audio with CD-DA compatibility, karaoke DSP.
BCKIN
LRCIN
DIN
ML
MC
MD
RSTB
Serial
Input
I/F
Mode
Control
I/F
8X Oversampling
Digital Filter
with Function
Controller
Multi-level
Delta-Sigma
Modulator
Multi-level
Delta-Sigma
Modulator
384fS
PLL2
PLL1
BPZ-Cont.
OSC
DAC
DAC
Low-pass
Filter
Low-pass
Filter
Open Drain
Power Supply
VOUTL
CAP
VOUTR
ZERO
SCKO3 SCKO2 SCKO1
MCKO XT1 XT2
VCP PGND VCA AGND VDD DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1997 Burr-Brown Corporation
PDS-1407A
Printed in U.S.A. September, 1997
1 page  
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
0
–20
–40
–60
–80
–100
0 0.4536fS
1.3605fS 2.2675fS
Frequency (Hz)
3.1745fS
4.0815fS
0
–0.2
–0.4
–0.6
–0.8
–1
0
PASSBAND RIPPLE CHARACTERISTIC
0.1134fS
0.2268fS
0.3402fS
Frequency (Hz)
0.4535fS
0
–2
–4
–6
–8
–10
–12
0
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
5k 10k 15k 20k 25k
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
0
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
5k 10k 15k 20k 25k
Frequency (Hz)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
DE-EMPHASIS ERROR (44.1kHz)
4999.8375 9999.675 14999.5125
Frequency (Hz)
19999.35
DE-EMPHASIS ERROR (48kHz)
5442
10884
Frequency (Hz)
16326
21768
®
5 PCM1727
5 Page 
when LRCIN is in a “HIGH” phase and right channel data
is assumed when LRCIN is in a “LOW” phase. When bit
1 is “HIGH”, the polarity assumption is reversed.
Bit 2 (ATC) is used for controlling the attenuator. When
bit 2 is “HIGH”, the attenuation data loaded in program
Register 0 is used for both left and right channels. When
bit 2 is “LOW”, the attenuation data for each register is
applied separately to left and right channels.
Bits 4 (DSR0) and 5 (DSR1) are used to control multiples
of the sampling rate:
DSR1
0
0
1
1
DSR0
0
1
0
1
Normal
Double
Reserved
Reserved
Multiple
44.1/48kHz
96kHz
Reserved
Reserved
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency:
SF1 SF0
00
01
10
11
Sampling Frequency
44.1kHz group
48kHz group
Reserved
Reserved
44.1kHz
48/96kHz
Reserved
Reserved
Bit 8 is used to control the infinite zero detection function
(IZD).
When IZD is “LOW”, the zero detect circuit is off. Under
this condition, no automatic muting will occur if the input
is continuously zero. When IZD is “HIGH”, the zero detect
feature is enabled. If the input data is continuously zero for
65, 536 cycles of BCKIN, the output will be immediately
forced to a bipolar zero state (VCC/2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero,
there may be an audible click. PCM1727 allows the zero
detect feature to be disabled so the user can implement an
external muting circuit.
ML (pin 7)
MC (pin 8)
MD (pin 9)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 8. Three-Wire Serial Interface.
ML
tMCH
tMCL
MC
tMCY
tMLH
tMLH
tMLS
tMLL
LSB
MD
tMDS
tMDH
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Setup Time
MD Hold Time
ML Low Level Time
ML High Level Time
ML Setup Time
ML Hold Time
SYSCLK: 1/384fS
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMLH
tMLS
tMLH
100ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns + 1SYSCLK (min)
40ns + 1SYSCLK (min)
40ns (min)
40ns (min)
FIGURE 9. Program Register Input Timing.
1.4V
1.4V
1.4V
11 PCM1727
®
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet PCM1727.PDF ] | |
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