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PDF ZN449E Data sheet ( Hoja de datos )
| Número de pieza | ZN449E | |
| Descripción | 8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ZN449E (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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ZN448/ZN449
8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER
DS3013 - 2.2
The ZN448 and ZN449 are 8-bit successive
approximation A-D converters designed to be easily
interfaced to microprocessors. All active circuitry is contained
on-chip including a clock generator and stable 2.5V bandgap
reference, control logic and double buffered latches with
reference.
Only a reference resistor and capacitor, clock resistor and
capacitor and input resistors are required for operation with
either unipolar or bipolar input voltage.
FEATURES
s Easy Interfacing to Microprocessor, or operates as a
'Stand-Alone' Converter
s Fast: 9 microseconds Conversion time Guaranteed
s Choice of Linearity: 0.5 LSB - ZN448, 1 LSB - ZN449
s On-Chip Clock
s Choice of On-Chip or External Reference Voltage
s Unipolar or Bipolar Input Ranges
s Commercial Temperature Range
ORDERING INFORMATION
Device type
Linearity Operating
error (LSB) temperature
ZN448E
0.5 0°C to +70°C
ZN449D
1 0°C to +70°C
ZN449E
1 0°C to +70°C
Package
DP18
MP18
DP18
BUSY (END OF CONVERSION) 1
RD (OUTPUT ENABLE) 2
CLOCK 3
WR (START CONVERSION) 4
REXT 5
VIN
VREF IN
6
7
VREF OUT 8
GROUND 9
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
10 +VCC (+5V)
ZN448/9E (DP18)
BUSY (END OF CONVERSION)
RD (OUTPUT ENABLE)
CLOCK
WR (START CONVERSION)
REXT
VIN
VREF IN
VREF OUT
GROUND
1
2
3
4
5
6
7
8
9
ZN449D (MP18)
18
17
16
15
14
13
12
11
10
Fig.1 Pin connection - top view
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)
+VCC (+5V)
ANALOGUE
INPUT
VREF IN
6
7
8
VREF OUT
2.5V
REFERENCE
8-BIT DAC
GROUND 9
VCC (+5V) 10
SUCCESSIVE
APPROXIMATION REGISTER
3-STATE BUFFERS
11 12 13 14 15 16 17 18
DB7
DB0
Fig.2 System diagram
COMPARATOR
+
-
5
REXT
CLOCK
GENERATOR
INTERFACE
AND
CONTROL
LOGIC
3 CK RC OR
EXT CLOCK
4
WR
1
BUSY
2
RD
1 page  
ZN448/9
If a free-running conversion is required, then the converter can
be made to cycle by inverting the BUSY output and feeding it
to WR. To ensure that the converter starts reliably after power-
up an initial start pulse is required. This can be ensured by
using a NOR gate instead of an inverter and feeding it with a
positive-going pulse which can be derived from a simple RC
network that gives a single pulse when power is applied, as
shown in Fig.4a.
The ADC will complete a conversion on every eighth clock
pulse, with the BUSY output going high for a period
determined by the propagation delay of the NOR gate, during
which time the data can be stored in a latch. The time available
for storing data can be increased by inserting delays into the
inverter path.
A timing diagram for the continuous conversion mode is
shown in Fig.3b.
As the BUSY output uses a passive pull-up the rise time of this
output depends on the RC time constant of the pull-up resistor
and load capacitance. In the continuous conversion mode the
use of a 4k7 external pull-up resistor is recommended to
reduce the risetime and ensure that a logic 1 level is reached.
Fig.4a Circuit for continuous conversion
Fig.4b Timing for continuous conversion
DATA OUTPUTS
The data outputs are provided with three-state buffers to allow
connection to a common data bus. An equivalent circuit is
shown in Fig.5. Whilst the RD input is high both output
transistors are turned off and the ZN448/9 presents only a high
impedance load to the bus.
When RD is low the data outputs will assume the logic states
present at the outputs of the successive register.
A test circuit and timing diagram for the output enable/disable
delays are given in Fig.6.
5
5 Page 
ZN448/9
Several suitable circuits are shown in Fig.13. The principle of
operation is the same in each case. Whilst the BUSY output
is high, capacitor C1 is charged to about 4-4.5V. During a
conversion the BUSY output goes low and the upper end of C1
is thus also pulled low. The lower end of C1 therefore applies
about -4V to R2, thus providing the tail current for the
comparator. The time constant R2. C1 is chosen according
to the clock frequency so that droop of the capacitor voltage is
not significant during a conversion.
The constraint on using this type of circuit is that C1 must be
recharged whilst the BUSY output is high. If the BUSY output
is high for greater than one converter clock period then the
circuit of Fig.13a will suffice. If this is not the case, for example,
in the continuous conversion mode, then the circuits of Figs.
13b and 13c are recommended, since these can pump more
current into the capacitor.
Where several ZN448/9's are used in a system the self-
oscillating diode pump circuit Fig.14 is recommeded.
Alternatively, if a negative supply is available in the system
then this may be utilised. A list of suitable resistor values for
different supply voltages is given in Table 1.
330
22n
5V
470
100n
IN914
IN914
-3.5V
100n
Fig.14 Diode pump circuit to supply comparator tail current for up to five ZN448/9's
V – (volts)
3
5
10
12
15
20
25
30
Table 1
REXT (kΩ)
47
82
150
180
220
330
390
470
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ZN449E.PDF ] | |
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