PDF PCK2023DL Data sheet ( Hoja de datos )

Número de pieza	PCK2023DL
Descripción	CK408 66/100/133/200 MHz spread spectrum differential system clock generator
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS PCK2023 CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator Product data File under Integrated Circuits — ICL03 2001 Sep 07 Philips Semiconductors 1 page Philips Semiconductors CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator Product data PCK2023 FREQUENCY SELECT/FUNCTION TABLE S2 S1 S0 CPU 3V66 66BUFF/ 3V66 66In/ 3V66_5 PCIF/PCI REF 0 USB/DOT 3V66_1/ VCH 100 66 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 101 100 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 110 200 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 111 133 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 000 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 66/48 MHz 001 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 66/48 MHz 010 200 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 66/48 MHz 011 133 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 66/48 MHz Mid 0 0 Low Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi-Z Mid 0 1 Tclk/2 Tclk/4 Tclk/4 Tclk/4 Tclk/8 Tclk Tclk/2 NOTE: 1. Mid is defined as a voltage level between 1.0 V and 1.8 V for 3 level input functionality. Low is below 0.8 V. High is above 2.0 V. 2. 3V66_1/VCH output frequency is set by the I2C. 3. Frequency of the 48 MHz outputs must be +167 ppm to match USB default. 4. Rref output min = 14.316 MHz, nominal = 14.31818, max = 14.32 MHz. 5. Tclk is a test clock over-driven on the XTAL_In input during test mode. Tclk/4 POWER DOWN MODE PWRDWN CPU 1 Normal 0 Iref2 CPU Normal Float 3V66 Normal Low 66BUFF/ 3V66 Normal Low 66In/ 3V66_5 Normal Low PCIF/PCI Normal Low REF 0 Normal Low USB/DOT Normal Low 3V66_1/ VCH Normal Low HOST SWING SELECT FUNCTIONS – CK408 MULT 0 BOARD IMPEDANCE Iref 0 50 Ω Rref = 221.1% Iref = 5.00 mA 1 50 Ω Rref = 475.1% I ref = 2.32 mA IOH IOH = 4Iref IOH = 6*Iref VOH @ 50 W 1.0 V 0.7 V IOUT IOUT CONDITIONS VDD = 3.3 V VDD = 3.3 V ±5% CONFIGURATION All combinations, see Table above All combinations, see Table above LOAD Nominal test load for given configuration Nominal test load for given configuration MIN. –7% of IOH See Table above –12% of IOH See Table above MAX. +7% of IOH See Table above +12% of IOH See Table above 2001 Sep 07 5 5 Page Philips Semiconductors CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator Product data PCK2023 CPU 1.0 V AC TIMING REQUIREMENTS SYMBOL PARAMETER TPERIOD tABSMIN average period absolute minimum host clock period Diff-tRISE Diff-tFALL SE ∆SKEW rise time fall time Absolute single-ended rise/fall waveform symmetry VCROSS absolute crossing point voltages tCCJITTER cycle-to-cycle jitter Duty Cycle — SE-VOH maximum voltage allowed at output SE-VOL minimum voltage allowed at output Diff- VRING_RISE Diff- VRING_FALL rising edge ringback falling edge ringback CPU 200 MHz MIN MAX 5.0 5.1 4.85 — 175 467 175 467 — 325 0.51 0.76 — 150 45 55 .92 1.45 –200 350 0.35 — — –0.35 CPU 133 MHz MIN MAX 7.5 7.65 7.35 — 175 467 175 467 — 325 0.51 76 — 150 45 55 .92 1.45 –200 350 0.35 — — –0.35 CPU 100 MHz MIN MAX 10.0 10.2 9.85 — 300 467 175 467 — 325 0.51 76 — 150 45 55 .92 1.45 –200 350 0.35 — — –0.35 CPU 66 MHz MIN MAX 15.0 15.3 UNITS NOTES ns 1, 15 14.85 — ns 1, 15 300 467 ps 15, 16 175 467 ps 15, 16 — 325 ps 17, 18 — — V 18 — 150 ps 15, 19 45 55 % 15 .92 1.45 V 18 –200 350 mV 18 0.35 — — –0.35 V V 15 15 2001 Sep 07 11 11 Page

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