PDF PCK2020 Data sheet ( Hoja de datos )

Número de pieza	PCK2020
Descripción	CK00 100/133MHz spread spectrum differential system clock generator
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS PCK2020 CK00 (100/133MHz) spread spectrum differential system clock generator Product specification Supersedes data of 2000 Jul 25 2000 Nov 13 Philips Semiconductors 1 page Philips Semiconductors CK00 (100/133MHz) spread spectrum differential system clock generator Product specification PCK2020 FUNCTION TABLES SEL 100/133 SELA SELB HOST MREF 3V66 3V33 PCI 48 MHz 0 0 0 100 MHz 50 MHz 66.7 MHz 33.3 MHz 48 MHz 0 0 1 105 MHz1 52.5 MHz1 70 MHz1 35 MHz1 48 MHz 0 1 0 200 MHz 50 MHz 66.7 MHz 33.3 MHz N/A 0 1 1 HI-Z HI-Z HI-Z HI-Z HI-Z 1 0 0 133 MHz 66.7 MHz 66.7 MHz 33.3 MHz 48 MHz 1 0 1 126.7 MHz1 63.3 MHz1 63.3 MHz1 31.7 MHz1 48 MHz 1 1 0 200 MHz 66.7 MHz 66.7 MHz 33.3 MHz 48 MHz 1 1 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 NOTE: 1. These frequencies are for debug and thus can vary a small amount from the values listed at the vendor’s discretion. SEL 100/133 0 0 0 0 1 1 1 1 SELA 0 0 1 1 0 0 1 1 SELB 0 1 0 1 0 1 0 1 Active 100 MHz Active 100 MHz – ~5% over-clock 200 MHz, 50 MHz MREF HI-Z all outputs Active 133 MHz Active 133.3 MHz minus ~5 under-clock 200 MHz, 66 MHz MREF Test mode HOST REF 14.318 MHz 14.318 MHz N/A HI-Z 14.318 MHz 14.318 MHz 14.318 MHz TCLK POWER DOWN MODE PWRDWN HOST/HOST_BAR MREF/MREF_B 3V66 PCI 48 MHz Asserts low 0 = Active HOST = 2IREF HOST_BAR LOW LOW LOW LOW NOTE: 1. The differential outputs should have a voltage forced across them when power down is asserted. REF OFF 14.318/66 MHz Seeds LOW/(if applicable) SPREAD SPECTRUM FUNCTION TABLE SPREAD FUNCTION 1 HOST/PCI/3V66/MREF/MREF_B No spread 0 HOST/PCI/3V66/MREF/MREF_B Down spread –0.5% 48 MHz PLL REF/MULTSEL0 REF/MULTSEL1 No spread No spread 2000 Nov 13 5 5 Page Philips Semiconductors CK00 (100/133MHz) spread spectrum differential system clock generator Product specification PCK2020 GROUP OFFSET LIMITS GROUP OFFSET MEASUREMENT LOADS (LUMPED) MEASURE POINTS NOTES 3V66 to PCI 1.5–3.5 ns 3V66 leads 3V66 @ 30 pf PCI @ 30 pf 3V66 @ 1.5 V PCI @ 1.5 V 19, 20 NOTES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset and skew measured on rising edge @ 1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks. 3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz. 4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided by three at Host = 100 MHz. 5. THKH is measured at 2.0 V for 2.5 V outputs and 2.4 V for 3.3 V outputs as shown in Figure 7. 6. THKL is measured at 0.4 V for all outputs as shown in Figure 7. 7. The time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 9. The average period over any 1 µs period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure duty-cycle specification is met. 11. Test load is Rs = 33.2 Ω, Rp = 49.9 Ω. 12. Must be guaranteed in a realistic system environment. 13. Configured for VOH = 0.71 V in a 50 Ω environment. 14. Measured at crossing points. 15. Measured at 20% to 80%. 16. Determined as a fraction of 2 (Trp–Trn)/(Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge. 17. Voltage measure point (Vm = 1.25 V). VDD = 2.5 V. 18. Voltage measure point (Vm = 1.5 V). VDD = 3.3 V. 19. All offsets are to be measured at rising edges. 20. Parameters are guaranteed by design. 2000 Nov 13 11 11 Page

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