|
|
PDF WT60P1 Data sheet ( Hoja de datos )
| Número de pieza | WT60P1 | |
| Descripción | Digital Monitor Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de WT60P1 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
|
No Preview Available !
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
GENERAL DESCRIPTION
The WT60P1 is a MTP (Multiple-Time-Programmable) version of WT60xx microcontroller which is
specially designed for digital controlled multi-sync monitor. It contains 8-bit CPU, 16K bytes flash
memory, 288 bytes RAM, 14 PWMs, parallel I/O, SYNC processor, timer, one DDC interface (slave
mode I2C interface with DDC1), one master/slave I2C interface, two 4-bit A/D converters and watch-
dog timer.
FEATURES
* 8-bit 6502 compatible CPU, 4MHz operating frequency
* 16384 bytes flash memory, 288 bytes SRAM
* 8MHz crystal oscillator
* 14 channels 8-bit/62.5kHz PWM outputs (8 open drain outputs & 6 CMOS outputs)
* Sync signal processor with H+V separation, frequency calculation, H/V polarity detection/control
* Three free-running sync signal outputs for burn-in test (64kHz/62.5Hz, 48kHz/75Hz, 31kHz/60Hz)
* Self-test pattern generator generates cross hatch picture
* DDC interface supports VESA DDC1/DDC2B standard
* Master/slave I2C interface
* Watch-dog timer (0.524 second)
* Maximum 25 programmable I/O pins
* One 8-bit programmable timer
* Two 4-bit A/D converter
* One external interrupt request
* Built-in low VDD voltage reset
* +5V power supply
PIN CONFIGURATION
40-Pin PDIP
42-Pin SDIP
DA2
DA1
DA0
RESET/VPP
VDD
GND
OSCO
OSCI
PB5/SDA2
PB4/SCL2
PB3/PAT
PB2
PB1/HLFI
PB0/HLFO
PB6/IRQ
PC7
PC6
PC5
PC4
PC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSYNC
DA2 1
39 HSYNC
DA1 2
38 DA3
DA0 3
37 DA4
RESET/VPP 4
36 DA5
VDD 5
35 DA6
6
34 DA7
GND 7
33 PA7/HSO
OSCO 8
32 PA6/VSO
OSCI 9
31 PA5/DA13 PB5/SDA2 10
30 PA4/DA12 PB4/SCL2 11
29 PA3/DA11 PB3/PAT 12
28 PA2/DA10
PB2 13
27 PA1/DA9
PB1/HLFI 14
26 PA0/DA8 PB0/HLFO 15
25 SCL1/PD0 PB6/IRQ 16
24 SDA1/PD1
PC7 17
23 PC0/AD0
PC6 18
22 PC1/AD1
PC5 19
21 PC2
PC4 20
PC3 21
42 VSYNC
41 HSYNC
40 DA3
39 DA4
38 DA5
37
36 DA6
35 DA7
34 PA7/HSO
33 PA6/VSO
32 PA5/DA13
31 PA4/DA12
30 PA3/DA11
29 PA2/DA10
28 PA1/DA9
27 PA0/DA8
26 SCL1/PD0
25 SDA1/PD1
24 PC0/AD0
23 PC1/AD1
22 PC2
* I2C is a trademark of Philips Corporation.
* DDC is a trademark of Video Electronics Standard Association (VESA).
Weltrend Semiconductor, Inc.
1
1 page  
I/O Ports
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
Port_A :
Pin PA0/DA8
Pin PA1/DA9
Pin PA2/DA10
Pin PA3/DA11
Pin PA4/DA12
Pin PA5/DA13
Pin PA6/VSO
Pin PA7/HSO
- general purpose I/O shared with DA8 output.
- general purpose I/O shared with DA9 output.
- general purpose I/O shared with DA10 output.
- general purpose I/O shared with DA11 output.
- general purpose I/O shared with DA12 output.
- general purpose I/O shared with DA13 output.
- general purpose I/O shared with VSYNC output.
- general purpose I/O shared with HSYNC output.
Port_A is controlled by REG#10H & REG#11H. In REG#10H, each corresponding bit enables
HSYNC output, VSYNC output or D/A converter output when it is "1". If the corresponding bit is "0",
the output level is decided by REG#11H. In REG#11H, if the I/O corresponding bit (PAn) is "0", the
output is low level (IOL=5mA). If PAn bit is "1", the output is high level (IOH= -100uA) and can be
used as an input.
Address
0010H
0011H
0011H
R/W
W
W
R
Initial
00H
FFH
--
Bit7
EHO
PA7W
PA7R
Bit6
EVO
PA6W
PA6R
Bit5
EDA13
PA5W
PA5R
Bit4
EDA12
PA4W
PA4R
Bit3
EDA11
PA3W
PA3R
Bit2
EDA10
PA2W
PA2R
Bit1
EDA9
PA1W
PA1R
Bit0
EDA8
PA0W
PA0R
Bit Name
Bit value = “1”
Bit value = “0”
EHO
Enable PA7 as HSYNC output.
PA7 as general purpose I/O.
EVO
Enable PA6 as VSYNC output.
PA6 as general purpose I/O.
EDA13
Enable PA5 as DA13 output.
PA5 as general purpose I/O.
EDA12
Enable PA4 as DA12 output.
PA4 as general purpose I/O.
EDA11
Enable PA3 as DA11 output.
PA3 as general purpose I/O.
EDA10
Enable PA2 as DA10 output.
PA2 as general purpose I/O.
EDA9
Enable PA1 as DA9 output.
PA1 as general purpose I/O.
EDA8
Enable PA0 as DA8 output.
PA0 as general purpose I/O.
PA7W - PA0W Outputs high level (IOH= -100uA).
PA7R- PA0R Pin is high level.
Outputs low level (IOL= 5mA).
Pin is low level.
* If the program wants to force VSYNC output (VSO pin) in low state, write "0" to PA6 bit first, then
write "0" to EVO bit. This is used to prevent high frequency output on VSO pin when the VSYNC
frequency is increased to read EDID data in DDC1 mode.
EDAx
DAx
PAnW
5mA
100uA
5mA
Pin PAn
PAnR
Weltrend Semiconductor, Inc.
5
5 Page 
Half Frequency
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
HLFO pin outputs same or half frequency from HLFI pin. The divide-by-2 operation is done on the
falling edge of HLFI pin when HALF bit is set. Polarity of HLFO is specified by HLFPO bit.
HLFI
HLFO
(HALF=0)
(HLFPO=0)
HLFO
(HALF=0)
(HLFPO=1)
HLFO
(HALF=1)
0016H
0016H
0017H
0017H
R/W
W
R
W
R
Initial
--
--
--
00H
Bit7
0
F9
--
H/V
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0 ENPAT PAT1 PAT0 SELF H64K H48K
F8 F7 F6 F5 F4 F3 F2
-- ENHLF HALF HLFPO H+V HOP VOP
-- H_POL V_POL OVF2 OVF1 F1
F0
Bit Name
ENPAT
PAT1,PAT0
SELF
H64K, H48K
ENHLF
HALF
HLFPO
H+V
HOP
VOP
H/V
H_POL
V_POL
OVF2, OVF1
F9-F0
Bit value = “1”
Bit value = “0”
Pin PB3/PAT outputs test pattern. Pin PB3/PAT is I/O port.
If PAT1=0, PAT0=0, cross hatch picture.
If PAT1=0, PAT0=1, white picture.
If PAT1=1, PAT0=0, inverted cross hatch picture.
If PAT1=1, PAT0=1, black picture.
HSO and VSO output free-running HSO and VSO output sync signals.
frequency.
H64K=“1”,H48K=“1” : Burn-in frequency=47.9kHz/74.9Hz
H64K=“0”,H48K=“1” : Burn-in frequency=47.9kHz/74.9Hz
H64K=“1”,H48K=“0” : Burn-in frequency=64kHz/62.5Hz
H64K=“0”,H48K=“0” : Burn-in frequency=31.1kHz/60.8Hz
Pin PB1/HLFI is frequency input. Pin PB1/HLFI and PB0/HLFO is I/O
Pin PB0/HLFO is half frequency
output.
port.
HLFO outputs half frequency of HLFI. HLFO outputs same frequency of HLFI
HLFO is positive polarity.
HLFO is negative polarity.
Enable H+V separation function.
Disable H+V separation.
This will select the sync signals come
from the sync separator.
HSO pin is always positive polarity. HSO pin is always negative polarity.
VSO pin is always positive polarity. VSO pin is always negative polarity.
Counter stores horizontal frequency. Counter stores vertical frequency.
HSYNC input is positive polarity. HSYNC input is negative polarity.
VSYNC input is positive polarity. VSYNC input is negative polarity.
OVF2=“1”,OVF1=“0” : Counter overflowed twice.
OVF2=“0”,OVF1=“1” : Counter overflowed once.
OVF2=“0”,OVF1=“0” : No overflow.
OVF2=“1”,OVF1=“1” : No such condition.
Frequency counter value. (F9 is MSB)
Weltrend Semiconductor, Inc.
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet WT60P1.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| WT60P1 | Digital Monitor Controller | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |