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PDF WM8972L Data sheet ( Hoja de datos )
| Número de pieza | WM8972L | |
| Descripción | MONO CODEC FOR PORTABLE AUDIO APPLICATIONS | |
| Fabricantes | Wolfson Microelectronics plc | |
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WM8972L
Mono CODEC for Portable Audio Applications
DESCRIPTION
The WM8972L is a low power, high quality mono CODEC
designed for portable digital audio applications.
The device integrates complete interfaces to mono
microphones. External component requirements are
drastically reduced as no separate microphone amplifiers
are required. Advanced on-chip digital signal processing
performs graphic equaliser and automatic level control for
the microphone or line input.
The WM8972L can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
The WM8972L operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
The WM8972L is supplied in a very small and thin 5x5mm
QFN package, ideal for use in hand-held and portable
systems.
BLOCK DIAGRAM
FEATURES
• DAC SNR 98dB (‘A’ weighted), THD –84dB at 48kHz, 3.3V
• ADC SNR 95dB (‘A’ weighted), THD -82dB at 48kHz, 3.3V
• Complete Mono Microphone Interface
- Programmable ALC / Noise Gate
• On-chip 400mW BTL Speaker Driver (mono)
• Digital Graphic Equaliser
• Low Power
- 7mW mono playback (1.8V / 1.5V supplies)
- 14mW record & playback (1.8V / 1.5V supplies)
• Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
• 256fs / 384fs or USB master clock rates: 12MHz, 24MHz
• Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
• 5x5x0.9mm QFN package
APPLICATIONS
• Digital Still Cameras
• Toys
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Preliminary Technical Data, June 2004, Rev 2.2
Copyright 2004 Wolfson Microelectronics plc
1 page  
Preliminary Technical Data
WM8972L
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Supply voltages
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, TA
Storage temperature after soldering
MIN
-0.3V
DGND -0.3V
AGND -0.3V
-25°C
-65°C
Notes
1. Analogue and digital grounds must always be within 0.3V of each other.
2. All digital and analogue supplies are completely independent from each other.
3. DCVDD must be less than or equal to AVDD & DBVDD.
MAX
+3.63V
DBVDD +0.3V
AVDD +0.3V
+85°C
+150°C
RECOMMENDED OPERATION CONDITIONS
PARAMETER
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Ground
SYMBOL
MIN
TYP
MAX
UNIT
DCVDD
1.42 2.0
3.6
V
DBVDD
1.8 2.0 3.6
V
AVDD, OPVDD
1.8 2.0 3.6
V
DGND,AGND, OPGND
0
V
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PTD Rev 2.2 June 2004
5
5 Page 
Preliminary Technical Data
CONTROL INTERFACE TIMING – 3-WIRE MODE
CSB
tCSL
SCLK
tSCY
tSCH
tSCL
tSCS
tCSH
tCSS
WM8972L
SDIN
tDSU
tDHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN TYP MAX UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
tSCS
80
ns
SCLK pulse cycle time
tSCY 200
ns
SCLK pulse width low
tSCL 80
ns
SCLK pulse width high
tSCH
80
ns
SDIN to SCLK set-up time
tDSU
40
ns
SCLK to SDIN hold time
tDHO
40
ns
CSB pulse width low
tCSL 40
ns
CSB pulse width high
tCSH
40
ns
CSB rising to SCLK rising
tCSS
40
ns
Pulse width of spikes that will be suppressed
tps
5
ns
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PTD Rev 2.2 June 2004
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8972L.PDF ] | |
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