PDF WM8751L Data sheet ( Hoja de datos )

Número de pieza	WM8751L
Descripción	STEREO DAC FOR PORTABLE AUDIO APPLICATIONS
Fabricantes	Wolfson Microelectronics plc
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No Preview Available ! WM8751L STEREO DAC FOR PORTABLE AUDIO APPLICATIONS DESCRIPTION The WM8751L is a low power, high quality stereo DAC with integrated headphone and loudspeaker amplifiers, designed to reduce external component requirements in portable digital audio applications. The on-chip headphone amplifiers can deliver 40mW into a 16Ω load. Advanced on-chip digital signal processing performs bass and treble tone control. The WM8751L can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices or standard 256fs rates like 12.288MHz and 24.576MHz. Different audio sample rates such as 96kHz, 48kHz, 44.1kHz are generated directly from the master clock without the need for an external PLL. The WM8751L operates on supply voltages from 1.8V up to 3.6V, although the digital core can operate on a separate supply down to 1.42V, saving power. Different sections of the chip can also be powered down under software control. The WM8751L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems. FEATURES • DAC SNR 98dB, THD -95dB (‘A’ weighted @ 48kHz, 3.3V) • On-chip 400mW BTL Speaker Driver (mono) • On-chip Headphone Driver ° 40mW output power on 16Ω / 3.3V ° THD –80dB at 20mW, SNR 90dB with 16Ω load • Stereo and Mono Line-in mix into DAC output • Separately Mixed Stereo and Mono Outputs • Digital Tone Control and Bass Boost • Low Power • Low Supply Voltages ° Analogue 1.8V to 3.6V ° Digital core: 1.42V to 3.6V ° Digital I/O: 1.42V to 3.6V • 256fs / 384fs or USB master clock rates: 12MHz, 24MHz • Audio sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock • 32-pin QFN package, 5x5x0.9mm size, 0.5mm lead pitch APPLICATIONS • Digital Audio Player • MP3 Phone • Minidisc Player BLOCK DIAGRAM CSB SDIN SCLK MODE BCLK DACLRC DACDAT MCLK DBVDD DCVDD DGND HPGND HPVDD CONTROL INTERFACE DIGITAL AUDIO INTERFACE W WM8751L DIFF. IN LEFT LD2LO MIXER LI2LO DIGITAL FILTERS DAC RD2LO MONO MIXER LD2MO MI2LO LI2MO TONE CONTROL DAC RD2MO RIGHT LD2RO MIXER RI2MO MI2RO RD2RO RI2RO VREF 50K 50K MONOOUT ROUT1 VREF M U X -1 OUT3 LOUT1VOL LOUT1 MONOVOL MONOOUT ROUT1VOL ROUT1 LOUT2 LOUT2VOL -1 ROUT2 INV ROUT2 ROUT2VOL Loudspeaker L - (-R) = L+R HPDETECT WOLFSON MICROELECTRONICS PLC www.wolfsonmicro.com Product Preview, May 2003, Rev 1.42 Copyright 2003 Wolfson Microelectronics Ltd. 1 page Product Preview WM8751L ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.5V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Line-Out (LOUT1/2, ROUT1/2, MONOOUT with 10kΩ / 50pF load) Signal to Noise Ratio SNR AVDD = 3.3V 98 dB (A-weighted) AVDD = 1.8V 95 Total Harmonic Distortion THD AVDD = 3.3V -95 dB AVDD = 1.8V -90 Channel Separation 1kHz signal 90 dB Analogue Mixer Inputs (LINEINL, LINEINR, MONOIN+) Full-scale Input Signal Level VINFS AVDD = 3.3V 1.0 V rms AVDD = 1.8V 0.516 Signal to Noise Ratio SNR AVDD = 3.3V 95 dB Line-in to Line-Out (A-weighted) AVDD = 1.8V 90 Total Harmonic Distortion THD AVDD = 3.3V -92 dB AVDD = 1.8V -92 dB Input Resistance RLINEIN PGA gain = 0dB 20 kΩ (signal enters one mixer only) PGA gain = +6dB 10 Input Resistance PGA gain = 0dB 10 (signal enters two mixers) PGA gain = +6dB 5 MONOIN- input resistance Programmable Gain RMONOIN- any gain 20 kΩ -15 +6 dB Programmable Gain Step Size Monotonic 3 dB Mute Attenuation TBD dB Analogue Outputs (LOUT1/2, ROUT1/2, MONOOUT) 0dB Full scale output voltage AVDD/3.3 Vrms Programmable Gain 1kHz signal -67 +6 dB Programmable Gain Steps Monotonic 80 steps Mute attenuation 1kHz, full scale signal 85 dB Channel Separation 80 90 dB Headphone Output (LOUT1/2, ROUT1/2 with 16 or 32 Ohm load) Output Power per channel Total Harmonic Distortion PO THD Output power is very closely correlated with THD; see below. HPVDD=1.8V, RL=32Ω PO=5mW 0.013 -78 dB % HPVDD=1.8V, RL=16Ω PO=5mW 0.013 -78 HPVDD=3.3V, RL=32Ω, PO=20mW 0.01 -80 HPVDD=3.3V, RL=16Ω, PO=20mW 0.01 -80 Signal to Noise Ratio SNR HPVDD = 3.3V 90 dB (A-weighted) HPVDD = 1.8V 90 w Product Preview Rev 1.42 May 2003 5 5 Page Product Preview WM8751L SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING tMCLKL MCLK tMCLKH tMCLKY Figure 1 System Clock Timing Requirements Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time SYMBOL tMCLKL tMCLKH tMCLKY MIN TYP MAX 16 16 27 UNIT ns ns ns AUDIO INTERFACE TIMING – MASTER MODE BCLK (Output) DACLRC (Output) DACDAT tDST tDHT tDL Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX System Clock Timing Information DACLRC propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold time from BCLK rising edge tDL tDST tDHT 10 10 10 UNIT ns ns ns BCLK DACLRC DACDAT AUDIO INTERFACE TIMING – SLAVE MODE tBCH tBCL tBCY tDS tLRH tLRSU Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface) w Product Preview Rev 1.42 May 2003 11 11 Page

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Número de pieza	Descripción	Fabricantes
WM8751L	STEREO DAC FOR PORTABLE AUDIO APPLICATIONS	Wolfson Microelectronics plc

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