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PDF W88113C Data sheet ( Hoja de datos )
| Número de pieza | W88113C | |
| Descripción | ATAPI CD-ROM DECODER & CONTROLLER | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W88113C
ATAPI CD-ROM
Decoder & Controller
1 page  
W88113C
ATAPI CD-ROM DECODER & CONTROLLER
1. OVERVIEW
1.1 Features
1.1.1 Host Interface
• Support ATAPI CD-ROM standard (SFF 8020)
• Ultra DMA/33 support to achieve high throughput and data integrity
• 32-byte Data FIFO to increase data throughput
• Support Block-offset transfer and Linear Address transfer
• Automatic ATAPI sequence handling
• Automatic data transfer trigger and cache management
1.1.2 DSP Interface
• Supports CD-ROM, CD-ROM/XA, CD-I, Video-CD, Photo-CD, and CD-Plus formats
• Supports various types of microprocessors and DSPs
• Supports CD-ROM data descrambling
• Supports both real-time correction and buffer-independent correction
• One byte error correction per P-word and Q-word
• Supports error detection of CD-ROM data
• Automatic repeated error correction
• Real time EDC checking logic
• Q-channel extraction by hardware to support precise CD-DA data reading
• Using pin BCK as subcode reference clock
• Target Search and Status Flag Collection to minimize micro-processor overhead
1.1.3 Microcontroller Interface
• Direct Register Addressing (default) and Indirect Register Addressing support
• Programmable ALE pin
• Support 2 programmable general I/O ports and one programmable general input port
Publication Release Date: Mar. 1999
- 1 - Revision 0.61
5 Page 
W88113C
DSP Interface
NAME
LRCK
NO.
8
SDATA 9
SDATA1 72
BCK
C2PO
10
11
TYPE
I
I
I
I
I
PIN DESCRIPTION
L/R Channel Clock - Left and right channels are distinguished by this
signal.
Serial Data - Serial data from DSP is received from this input.
Serial Data - Second Serial data from DSP is received from this
input.
Bit Clock - Bit clock from DSP is received from this input.
C2 Pointer - C2 error flag from DSP is received from this input.
Subcode Interface
NAME NO. TYPE
SCSD
17
I
WFCK 18
I
SCSYN
EXCK
19
20
I
I/O
PIN DESCRIPTION
Subcode Serial Data - Subcode serial data from DSP is received from
this input.
Write Frame Clock - Write frame clock from DSP is received from
this input.
Subcode Sync - Subcode sync from DSP is received from this input.
External Clock - A pin programmed as input or output to supply bit
clock for subcode.
External RAM Interface
NAME
ROEb
RWEb
RD[15:0]
RA[9:0]
CASH/L
RAS
NO.
84
88
12, 7, 24, 5, 4,
91, 94, 86, 78,
79, 77, 76, 81,
82, 87, 85
91, 92, 93, 95,
96, 97, 2, 100,
99, 98
3, 83
90
TYPE
O
O
I/O
O
O
O
PIN DESCRIPTION
External RAM Output Enable - A low-active output signal
External RAM Write Enable - A low-active output signal
RAM Data Bus - Data bus for external RAM.
RAM Address Bus - Address bus for external RAM.
External RAM Column Address Strobe
External RAM Row Address Strobe
Publication Release Date: Mar. 1999
- 7 - Revision 0.61
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W88113C.PDF ] | |
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