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PDF W83194R-39 Data sheet ( Hoja de datos )
| Número de pieza | W83194R-39 | |
| Descripción | 100MHZ 3-DIMM CLOCK | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W83194R-39/-39A
1.0 GENERAL DESCRIPTION
100MHZ 3-DIMM CLOCK
The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequency of
CPU and PCI clocks and W83194R-39A provides sixteen CPU/PCI frequencies which are externally
selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by
the none-delay buffer_in pin.
The W83194R-39/-39A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping
individual clock outputs and frequency selection through I2C interface. The device meets the
Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after
power-up. It is not recommend to use the dual function pin for the slots(ISA, PCI, CPU, DIMM). The
add on cards may have a pull up or pull down.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
• Supports Pentium™ II CPU with I2C.
• 2 CPU clocks (one free-running CPU clock)
• 13 SDRAM clocks for 3 DIMs
• 6 PCI synchronous clocks
• One IOAPIC clock for multiprocessor support
• Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
• < 250ps skew among CPU and SDRAM clocks
• < 250ps skew among PCI clocks
• < 5ns propagation delay SDRAM from buffer input
• Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
• Smooth frequency switch with selections from 50 MHz to 133 MHz CPU
• I2C 2-Wire serial interface and I2C read back
Publication Release Date: May 1998
- 1 - Revision 0.20
1 page  
W83194R-39/-39A
5.3 I2C Control Interface
SYMBOL
SDATA
PIN
23
SDCLK
24
PRELIMINARY
I/O FUNCTION
I/O Serial data of I2C 2-wire control interface with internal
pull-up resistor.
IN Serial clock of I2C 2-wire control interface with
internal pull-up resistor.
5.4 Fixed Frequency Outputs
SYMBOL
REF0 / PCI_STOP#
PIN
2
REF1 / *FS2
46
24MHz / *FS1
25
48MHz / *FS0
26
I/O FUNCTION
I/O 14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Halt PCICLK(0:4) clocks at logic 0 level, when input
low (In mobile mode. MODE=0)
I/O 14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
I/O 24MHz output clock.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
I/O 48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
5.5 Power Pins
SYMBOL
Vddq1
VddL1
VddL2
Vddq2
Vddq3
Vddq4
Vss
PIN FUNCTION
1 Power supply for Ref [0:1] crystal and core logic.
48 Power supply for IOAPIC output, either 2.5V or 3.3V.
42 Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
6, 14
Power supply for PCICLK_F, PCICLK[0:4], 3.3V.
19, 30, 36
Power supply for SDRAM[0:12], and CPU PLL core,
nominal 3.3V.
27 Power for 24 & 48MHz output buffers and fixed PLL
core.
3,9,16,22,33,39,45 Circuit Ground.
Publication Release Date: May 1998
- 5 - Revision 0.20
5 Page 
W83194R-39/-39A
8.3.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
Bit @PowerUp Pin
Description
7 1 - Reserved
6 1 7 PCICLK_F (Active / Inactive)
5 1 - Reserved
4 1 14 PCICLK4 (Active / Inactive)
3 1 12 PCICLK3 (Active / Inactive)
2 1 11 PCICLK2 (Active / Inactive)
1 1 10 PCICLk1 (Active / Inactive)
0 1 8 PCICLK0 (Active / Inactive)
PRELIMINARY
8.3.4 Register 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped )
Bit @PowerUp
Pin
Description
71
- Reserved
61
- Reserved
51
26 48MHz (Active / Inactive)
41
25 24MHz (Active / Inactive)
31
- Reserved
2 1 21,20,18,17 SDRAM(8:11) (Active / Inactive)
1 1 32,31,29,28 SDRAM(4:7) (Active / Inactive)
0 1 38,37,35,34 SDRAM(0:3) (Active / Inactive)
- 11 -
Publication Release Date: May 1998
Revision 0.20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet W83194R-39.PDF ] | |
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