PDF W78LE812P-24 Data sheet ( Hoja de datos )

Número de pieza	W78LE812P-24
Descripción	8-BIT MTP MICROCONTROLLER
Fabricantes	Winbond
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No Preview Available ! W78LE812 8-BIT MTP MICROCONTROLLER GENERAL DESCRIPTION The W78LE812 is an 8-bit microcontroller which can accommodate a wide range of supply voltages with low power consumption. The instruction set for the W78LE812 is fully compatible with the standard 8051. The W78LE812 contains an 8K bytes MTP ROM (Multiple-Time Programmable ROM); a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 6-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by a fourteen sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM inside the W78LE812 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78LE812 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES • Fully static design 8-bit CMOS microcontroller • Wide supply voltage of 2.4V to 5.5V • 256 bytes of on-chip scratchpad RAM • 8 KB electrically erasable/programmable MTP-ROM • 64 KB program memory address space • 64 KB data memory address space • Four 8-bit bi-directional ports • Three 16-bit timer/counters • Timer 2 Clock-out • One full duplex serial port(UART) • Watchdog Timer • Direct LED drive outputs • Fourteen sources, two-level interrupt capability • Wake-up via external interrupts at Port 1 • EMI reduction mode • Built-in power management • Code protection mechanism • Packages: − DIP 40: W78LE812-24 − PLCC 44: W78LE812P-24 − PQFP 44: W78LE812F-24 Publication Release Date: February 1999 - 1 - Revision A2 1 page W78LE812 setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. In the auto-reload mode, Timer 2 performs a up counter which is similar with standard 8052. When counting up, an overflow in Timer 2 will cause a reload from RCAP2H and RCAP2L registers. The Timer 2 also provides a programmable clock-out mode as a clock generator. To enable this mode, timer 2 has to be configured with a 16-bit auto-reload timer (C/T2 = 0, CP/RL2 = 0) and bit T2OE (T2MOD.1) must be set to 1. This mode produces a 50% duty cycle clock output and timer 2 roll- overs will not generate an interrupt. The clock-out frequency depends on the oscillator frequency and the reload value of registers RCAP2H and RCAP2L. The clock-out frequency is determined by following equation: Clock-out Frequency = Oscillator Frequency / [ 4 × ( 65536 - RCAP2H, RCAP2L ) ] OSC 1/2 TL2 TH2 1/2 T2 (P1.0) TR2 (T2CON.2) T2EX (P1.1) EXEN2 (T2CON.3) Timer 2 Clock-Out Mode RCAP2L RCAP2H EXF2 T2CON.6 Timer 2 Interrupt TIMER 2 MODE CONTROL Bit: 7 6 5 4 ---- Mnemonic: T2MOD 32 -- Address: C9h 1 T2OE 0 - T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function. I/O Port Options The Port 0 and Port 3 of W78LE812 may be configured with different types by setting the bits of the Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi- directional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a quasi-bi-directional I/O port with internal pull-up that is structurally the same as Port 2. The high nibble of Port 3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink about 20mA current for driving LED display directly. After reset, the POR register is cleared and the pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below. Publication Release Date: February 1999 - 5 - Revision A2 5 Page W78LE812 Clock The W78LE812 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78LE812 relatively insensitive to duty cycle variations in the clock. The W78LE812 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. AUXR - Auxiliary Register Bit: 7 6 5 4 3 2 1 0 -- -- - - - AO Mnemonic: AUXR Address: 8Eh AO: Turn off ALE signal. Reduce EMI Emission Because of the on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space.. Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78LE812 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. - 11 - Publication Release Date: February 1999 Revision A2 11 Page

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