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PDF W6810 Data sheet ( Hoja de datos )
| Número de pieza | W6810 | |
| Descripción | SINGLE-CHANNEL VOICEBAND CODEC | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W6810
SINGLE-CHANNEL VOICEBAND CODEC
www.DataSheet4U.com
Preliminary Data Sheet
Publication Release Date: October 10, 2002
- 1 - Revision A9
1 page  
W6810
12.1. 20L TSSOP – 4.4X6.5mm ..................................................................................................... 31
12.2. 20L SOP – 300mil.................................................................................................................. 32
12.3. 20L SSOP – 209mil ............................................................................................................... 33
12.4. 20L PDIP................................................................................................................................ 34
13. ORDERING INFORMATION........................................................................................................... 35
14. VERSION HISTORY ....................................................................................................................... 36
Publication Release Date: October 10, 2002
- 5 - Revision A9
5 Page 
W6810
7.4.1. Long Frame Sync
The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the
BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8
kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC
sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when
the FST pin is held high for two consecutive falling edges of the bit-clock at the BCLKT pin. The length
of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge
occurs every 125 µsec. During data transmission in the Long Frame Sync mode, the transmit data pin
PCMT will become low impedance when the Frame Sync signal FST is high or when the 8 bit data
word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame
Sync signal FST becomes low while the data is transmitted or when half of the LSB is transmitted. The
internal decision logic will determine whether the next frame sync is a long or a short frame sync,
based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high
impedance for two frame sync cycles after every power down state. More detailed timing information
can be found in the interface timing section.
7.4.2. Short Frame Sync
The W6810 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is high
for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the
bit-clock, the W6810 starts clocking out the data on the PCMT pin, which will also change from high to
low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway
the LSB. The Short Frame Sync operation of the W6810 is based on an 8-bit data word. When
receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge
that coincides with the Frame Sync signal. The internal decision logic will determine whether the next
frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus
collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down
state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
- 11 -
Publication Release Date: October 10, 2002
Revision A9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W6810.PDF ] | |
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