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PDF W6662CF Data sheet ( Hoja de datos )
| Número de pieza | W6662CF | |
| Descripción | SCANNER ANALOG FRONT END | |
| Fabricantes | Winbond | |
| Logotipo |  |
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Preliminary W6662CF
SCANNER ANALOG FRONT END
1. GENERAL DESCRIPTION
The W6662 is a highly integrated CCD/CIS analog front end signal processor. It provides the
components required for all necessary front-end signal process of a CCD/CIS scanner, including a 3-
channel input clamp circuit for correlated double sampling (short as CDS) mode, a multiplexer to mux
3-channel inputs to a correlated double sampling (CDS) circuit, a programmable offset adjusted and
gain controlled amplifier, a 12-bit analog-to-digital converter.
CDS or S&H (sample and hold) of operation modes can be chosen. The device configuration is
programmed via 3-wire or 4-wired interface, operation modes, offset and gain value of each channel
can be programmed.
2. FEATURES
• 12-bit A/D Converter
• No Missing Code Guaranteed
• Three channels analog input with clamp circuit individually
• Integrated Correlated Double Sampler (CDS)
• Supports Contact Image Sensors (CIS)
• Accept CCD/CIS sensor with three channel or single channel analog out
• External offset voltage input for CIS reference voltage
• Built-in bandgap reference circuit for CDS mode and A/D Converter
• Integrated 6-bit Programmable Gain Amplifier (PGA) with 3-channel register selected
• Integrated 8-bit offset adjustment with 3-channel register selected
• 3 MHz sampling rate of offset/gain adjustment circuit
• Three-wired or four-wired Serial Interface programmable
• Registers readback capability
• Low power CMOS device
• Power down mode supported
• 3/5V digital I/O pin
• Packageed in 48-pin QFP
Applications:
Flatbed Scanners
Sheetfeed Scanners
Film Scanners
Publication Release Date: December 1998
- 1 - Revision A1
1 page  
Preliminary W6662CF
If input capacitor value is specified as CIN, the following is the equation to calculate how many lines
are required before the capacitor settles to the desired accuracy after power is up:
LN =
(RON + RCCDS) × CIN
PIXN × tCLP
ln (VOFS/VCLPTolerance )
where
LN is line number.
PIXN is the total pixel number in one line.
CIN is the input capacitor value, 0.01 µF is suggestion value.
VOFS is the internal offset voltage to be clampped on the input terminal of the input capacitor.
CCD Device
RCCDS
CIN
IBIAS
W6662
Input to MUX
0.01uF
RON = 5K
on when
CDSCK1= high
VOFS
Fig. 6-1 Equivalent Circuit of Clampping.
Output
signal
from CCD
(Pixel n) VC
VDATAn
VOFS
Input
signal
to W6662
VC
VDATAn
(Pixel n+1)
VDATAn+1
tCLP
VCLPTolerance
VDATAn+1
Fig. 6-2 CCD Input Clamp Waveform.
6.2 MUX and Channel Select
The analog input signal may be three channels or single channel and is specified in configuration
register. Three channel input or single channel input are described as follows:
The three channel input is used for red, green and blue analog signal input, selected by SEL1 and
SEL0 signals. The channel select signals SEL1 and SEL0 may be 01, 10, 11 and listed as follows:
SEL1 = 0, SEL0 = 1 is red channel input selected, red channel of gain register and offset register also
selected.
SEL1 = 1, SEL0 = 0 is green channel input selected, green channel of gain register and offset register
also selected.
SEL1 = 1, SEL0 = 1 is blue channel input selected, blue channel of gain register and offset register
also selected.
SEL1 = 0, SEL0 = 0 is reserved.
The one channel input is used for black and white CCD/CIS sensor or multiplexed color CCD/CIS
sensor output. Any channel input of red, green or blue can be used, other un-used analog input must
tight to VSS in S & H mode. The channel select signals SEL1 and SEL0 is used to select offset
register and gain register only and may be 01, 10, 11, described as follows:
Publication Release Date: December 1998
- 5 - Revision A1
5 Page 
Preliminary W6662CF
7.4 Digital Characteristics, continued
PARAMETER
CONDITION SYM. MIN. TYP‡ MAX. UNITS NOTES
Schmitt Input Low Threshold (VDRVDD = 5V)
Voltage
VT-
0.8
V4
Input Current
Iin 1 µA
Input Capacitance
Cin 10 pF
‡: Typical figure are at VDD = 5V and temperature = 25° C and are for design aid only, not guaranteed and not subject to
production testing.
Notes:
1: VOH = 0.9 VDRVDD.
2: VOL = 0.1 VDRVDD.
3. All digital input pin, CDSCK1, CDSCK2, ADCCLK and SCLK are exclusive.
4. CDSCK1, CDSCK2, ADCCLK and SCLK schmitt trigger input pins.
7.5 Analog Characteristics (measures from analog input to ADC output)
PARAMETER
SYM. MIN. TYP‡ MAX. UNITS TEST CONDITIONS
Analog to Digital Converter
Maximum Conversion Rate
SPS
3
MHz
Resolution
12 Bits
Integral Nonlinearity
INL
+/- 4 LSB
Differential Nonlinearity
DNL
+/- 1 LSB
Gain Error
ADGERR
2.7% FSR
Note 1
Offset Error
ADOFERR
2.7% FSR
Note 1
PGA & Offset DAC
PGA Gain Range
G1
6.25 V/V
PGA Gain Resolution
GRES
64
steps
Note 2
Offset Range
OFS -200
200 mV
VAVDD = 5.0V
Offset Resolution
OFSRES
256
steps
Note 2
Bandgap Reference
Voltage Reference Tolerance
(VREF = 1.5V or 0.75V)
VREF
+/- +/-
1.5% 2.0%
VAVDD = 5.0V
Analog Input and Output
Linear Region of Analog Input Vin
0
3V
Input Capacitance
Cin 10 pF
Input Leakage Current
IBIAS
0.01 µA
Total Output Noise at PGA
4 LSB
- 11 -
Publication Release Date: December 1998
Revision A1
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet W6662CF.PDF ] | |
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