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PDF W27L010 Data sheet ( Hoja de datos )
| Número de pieza | W27L010 | |
| Descripción | 128K 8 ELECTRICALLY ERASABLE EPROM | |
| Fabricantes | Winbond | |
| Logotipo |  |
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Preliminary W27L010
128K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 131072 × 8 bits. It requires only one supply in the range of 3.0V to 3.6V in
normal read mode. The W27L010 provides an electrical chip erase function.
FEATURES
• High speed access time:
90/120 nS (max.)
• Read operating current: 10 mA (max.)
• Erase/Programming operating current:
30 mA (max.)
• Standby current: 20 µA (max.)
• Low voltage power supply range, 3.0V to 3.6V
• +14V erase/+12V programming voltage
• Fully static operation
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Available packages: 32-pin 600 mil DIP, 450
mil SOP and PLCC
PIN CONFIGURATIONS
Vpp
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8 32-pin DIP
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
PGM
NC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
/
AAA V V P
111 p c GN
2 56 p c MC
432 1 33 3
A7 5
2 1 0 29
A6 6
28
A5 7
27
A4 8
26
A3 9 32-pin PLCC 25
A2 10
24
A1 11
23
A0 12 1 1 1 1 1 1 2 22
Q0 13 4 5 6 7 8 9 0 21
Q QGQ QQQ
1 2 N3 4 5 6
D
A14
A13
A8
A9
A11
OE
A10
CE
Q7
BLOCK DIAGRAM
PGM
CE
OE
CONTROL
OUTPUT
BUFFER
Q0
.
.
Q7
A0
.
DECODER
.
A16
VCC
GND
VPP
CORE
ARRAY
PIN DESCRIPTION
SYMBOL
A0−A16
Q0−Q7
CE
OE
PGM
VPP
VCC
GND
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
No Connection
Publication Release Date: February 1999
- 1 - Revision A1
1 page  
Preliminary W27L010
CAPACITANCE
(VCC = 3.0V to 3.6V , TA = 25° C, f = 1 MHz)
PARAMETER
SYMBOL
Input Capacitance
CIN
Output Capacitance
COUT
CONDITIONS
VIN = 0V
VOUT = 0V
MAX.
6
12
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
CONDITIONS
0.45V to 2.4V
10 nS
0.8V/2.0V
CL = 100 pF,
IOH/IOL = -0.1 mA/1.6 mA
AC Test Load and Waveforms
+1.3V
(IN914)
3.3K ohm
D OUT
100 pF (Including Jig and Scope)
UNIT
pF
pF
Input
2.4V
0.45V
Test Points
2.0V
0.8V
Output
Test Points
2.0V
0.8V
Publication Release Date: February 1999
- 5 - Revision A1
5 Page 
Preliminary W27L010
SMART ERASE ALGORITHM
Start
X=0
Vcc = 5V
Vpp = 14V
A9 = 14V; A0 = V IL
Chip Erase 100 mS Pulse
Address = First Location
Increment X
Vcc = 2.7V
Vpp = 2.7V
Erase
Verify
Fail
Pass
Increment No Last
Address
Address?
Yes
Vcc = 3.3V
Vpp = 3.3V
Compare
All Bytes to
FFs (HEX)
Pass
Pass
Device
Fail
No
X = 20?
Yes
Fail
Device
- 11 -
Publication Release Date: February 1999
Revision A1
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet W27L010.PDF ] | |
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