PDF W25S243AD-12 Data sheet ( Hoja de datos )

Número de pieza	W25S243AD-12
Descripción	64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM
Fabricantes	Winbond
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No Preview Available ! Preliminary W25S243A 64K × 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium™ burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduces power dissipation. This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle. FEATURES • Synchronous operation • High-speed access time: 12 nS • Single +3.3V power supply • Individual byte write capability • 3.3V LVTTL compatible I/O • Clock-controlled and registered input • Asynchronous output enable • Pipelined/non-pipelined data output capability • Supports snooze mode (low-power state) • Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode • Supports 2T/1T mode • Packaged in 128-pin QFP and TQFP BLOCK DIAGRAM A(15:0) CLK CE(3:1) GW BWE BW(8:1) OE ADSC ADSP ADV LBO FT ZZ INPUT REGISTER CONTROL LOGIC REGISTER 64K X 64 CORE ARRAY DATA I/O REGISTER I/O(64:1) Publication Release Date: November 1998 - 1 - Revision A1 1 page Preliminary W25S243A Truth Table, continued CYCLE ADDRESS USED CE1 CE2 CE3 ADSP ADSC ADV OE DATA WRITE* Begin Write Current X X X 1 1 1 X Hi-Z Write Begin Write Current 1 X X X 1 1 X Hi-Z Write Begin Write External 0 1 0 1 0 X X Hi-Z Write Continue Write Next X X X 1 1 0 X Hi-Z Write Continue Write Next 1 X X X 1 0 X Hi-Z Write Suspend Write Current X X X 1 1 1 X Hi-Z Write Suspend Write Current 1 X X X 1 1 X Hi-Z Write Notes: 1. For a detailed definition of read/write, see the Write Table below. 2. An "X" means don't care, "1" means logic high, and "0" means logic low. 3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to the bus clock except for the OE pin. 4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings are met. WRITE TABLE READ/WRITE FUNCTION Read Read Write byte 1 I/O1−I/O8 Write byte 2 I/O9−I/O16 Write byte 2, byte 1 Write byte 3 I/O17−I/O24 Write byte 3, byte 1 Write byte 3, byte 2 Write byte 3, byte 2, byte 1 Write byte 4, I/O25−I/O32 Write byte 4, byte 1 Write byte 4, byte 2 Write byte 4, byte 2, byte 1 Write byte 4, byte 3 Write byte 4, byte 3, byte 1 Write byte 4, byte 3, byte 2 Write byte 4, byte 3, byte 2, byte 1 Write byte 5, I/O33−I/O40 Write byte 5, byte 1 GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1 1 1 XXXXXXXX 1011111111 1011111110 1011111101 1011111100 1011111011 1011111010 1011111001 1011111000 1011110111 1011110110 1011110101 1011110100 1011110011 1011110010 1011110001 1011110000 1011101111 1011101110 Publication Release Date: November 1998 - 5 - Revision A1 5 Page Preliminary W25S243A Timing Waveforms, continued Write Cycle Timing CLK ADSP ADSC ADV A[15:0] GW BWE BW[4:1] CE1 CE2 CE3 Single Write TADSS TADSH Burst Write TCYC TKH TKL Write Unselected ADSP is blocked by CE1 inactive TADCS TADCH TADVS TADVH ADSC initiated write TAS TAH ADV must be inactive for ADSP write WR1 WR2 WR3 TWS TWH GWE allows processor address (and BE=BW) to be pipelined during a writeback TWS TWH TCES TWS TWH WR1 TCEH WR2 WR3 CE1 masks ADSP TCES TCEH CE2 and CE3 only sampled with ADSP or ADSC TCES TCEH Unselected with CE2 OE Data-Out High-Z Data-In High-Z TDS TDH 1a DON'T CARE UNDEFINED BW[4:1] are applied only to first cycle of WR2 2a 2b 2c 2d 3a - 11 - Publication Release Date: November 1998 Revision A1 11 Page

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