PDF W194 Data sheet ( Hoja de datos )

Número de pieza	W194
Descripción	Frequency Multiplier and Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! W194 Frequency Multiplier and Zero Delay Buffer Features • Two outputs • Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs • Available in 8-pin SOIC package Key Specifications Operating Voltage: .............................. 3.3V±5% or 5.0±10% Operating Range: .......................10 MHz < fOUT1 < 133 MHz Absolute Jitter: ......................................................... ±500 ps Output to Output Skew: .............................................. 250 ps Propagation Delay: ................................................... ±350 ps Propagation delay is affected by input rise time. Block Diagram Table 1. Configuration Options FBIN OUT1 OUT1 OUT1 OUT1 OUT2 OUT2 OUT2 OUT2 FS0 FS1 OUT1 0 0 2 X REF 1 0 4 X REF 01 REF 1 1 8 X REF 0 0 4 X REF 1 0 8 X REF 0 1 2 X REF 1 1 16 X REF Pin Configuration OUT2 REF 2 X REF REF/2 4 X REF 2 X REF 4 X REF REF 8 X REF FBIN FS0 ÷Q FS1 External feedback connection to OUT1 or OUT2, not both FBIN IN GND FS0 SOIC 18 27 36 45 OUT2 VDD OUT1 FS1 IN Reference Input Phase Detector Charge Pump Loop Filter Output Buffer VCO ÷2 Output Buffer OUT1 OUT2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 5, 2000, rev. *A 1 page W194 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% Parameter Description Test Condition Min Typ Max Unit fIN fOUT Input Frequency[1] Output Frequency OUT2 = REF OUT1 15-pF load[6] 10 MHz 133 MHz tR Output Rise Time 2.0V to 0.8V, 15-pF load 3.5 ns tF Output Fall Time 2.0V to 0.8V, 15-pF load 2.5 ns tICLKR Input Clock Rise Time[2] 10 ns tICLKF Input Clock Fall Time[2] 10 ns tPD FBIN to REF Skew[3, 4] Measured at VDD/2 –2 0.6 2 ns tD Duty Cycle 15-pF load[5] 40 50 60 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle 300 ps AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 5.0V ±10% Parameter Description Test Condition Min Typ Max Unit fIN fOUT Input Frequency[1] Output Frequency OUT2 = REF OUT1 15-pF load[6] 10 MHz 133 MHz tR Output Rise Time 2.0V to 0.8V, 15-pF load 2.5 ns tF Output Fall Time 2.0V to 0.8V, 15-pF load 1.5 ns tICLKR Input Clock Rise Time[2] 10 ns tICLKF Input Clock Fall Time[2] 10 ns tPD FBIN to REF Skew[3, 4] Measured at VDD/2 –2 0.6 2 ns tD Duty Cycle 15-pF load[5, 7] 40 50 60 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle 200 ps Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V. 6. For the higher drive -11, the load is 20 pF. 7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case. Ordering Information Ordering Code W194 Document #: 38-00794-A Option -70 Package Name G Package Type 8-pin SOIC (150-mil) 5 5 Page

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