PDF W184-5 Data sheet ( Hoja de datos )

Número de pieza	W184-5
Descripción	Six Output Peak Reducing EMI Solution
Fabricantes	Cypress Semiconductor
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No Preview Available ! W184 Six Output Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS™ family offering • Generates an EMI optimized clocking signal at the output • Selectable input to output frequency • Six 1.25%, 3.75%, or 0% down or center spread outputs • One non-Spread reference output • Integrated loop filter components • Operates with a 3.3 or 5V supply • Low power CMOS design • Available in 24-pin SSOP (Shrunk Small Outline Package) • Outputs may be selectively disabled Key Specifications Supply Voltages: ........................................... VDD = 3.3V±5% or VDD = 5V±10% Frequency Range: .............................. 8 MHz ≤ Fin ≤ 28 MHz Crystal Reference Range.................... 8 MHz ≤ Fin ≤ 28 MHz Cycle to Cycle Jitter: ........................................ 300 ps (max.) Selectable Spread Percentage: ....................1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: .................................. 5 ns (max.) SS% 0 1 W184 Output Fin ≥ Fout ≥ Fin – 1.25% Fin ≥ Fout ≥ Fin – 3.75% W184-5 Output Fin + 0.625% ≥ Fin≥ – 0.625% Fin + 1.875% ≥ Fin≥ –1.875% Table 2. Frequency Range Selection FS2 FS1 00 01 10 11 Table 3. Output Enable Frequency Range 8 MHz ≤ FIN ≤ 10 MHz 10 MHz ≤ FIN ≤ 15 MHz 15 MHz ≤ FIN ≤ 18 MHz 18 MHz ≤ FIN ≤ 28 MHz EN1 0 0 1 EN2 0 1 0 CLK0:4 Low Low Active CLK5 Low Active Low 1 1 Active Active Simplified Block Diagram 3.3 or 5.0V XTAL Input X1 X2 W184 Spread Spectrum Outputs (EMI suppressed) 3.3 or 5.0V Oscillator or Reference Input W184 Spread Spectrum Outputs (EMI suppressed) Pin Configuration SSOP REFOUT FS2 X1 X2 GND SS% EN2 GND CLK0 VDD CLK1 CLK2 1 2 3 4 5 6 7 8 9 10 11 12 24 SSON# 23 RESET 22 FS1 21 VDD 20 VDD 19 NC 18 EN1 17 CLK5 16 VDD 15 CLK4 14 GND 13 CLK3 PREMIS is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 July 25, 2000, rev. *B 1 page W184 Absolute Maximum Ratings Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description VDD, VIN TSTG TB TA PD Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Power Dissipation above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Rating –0.5 to +7.0 –65 to +150 –55 to +125 0 to +70 0.5 Unit V °C °C °C W DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5% Parameter Description Test Condition IDD Supply Current tON Power Up Time First locked clock cycle after Power Good VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 1 IIH Input High Current Note 1 IOL Output Low Current @ 0.4V, VDD = 3.3V IOH Output High Current @ 2.4V, VDD = 3.3V CI Input Capacitance All pins except CLKIN CI Input Capacitance CLKIN pin only RP Input Pull-Up Resistor ZOUT Clock Output Impedance Note: 1. Inputs FS1:2, SS% have a pull-up resistor; Input SSON# has a pull-down resistor. Min. 2.4 2.4 –50 Typ. 18 15 15 6 500 25 Max. 32 5 0.8 0.4 50 7 10 Unit mA ms V V V V µA µA mA mA pF pF kΩ Ω 5 5 Page

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