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PDF VT82C42 Data sheet ( Hoja de datos )
| Número de pieza | VT82C42 | |
| Descripción | VT82C42 Keyboard Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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VT82C42
KEYBOARD CONTROLLER
Preliminary Release
DATE : November 22, 1995
VIA TECHNOLOGIES, INC.
1 page  
VIA Technologies, Inc.
VT82C42
4. Register
Table 1. Status register: read only (with A0 = 1, CS# = 0, RD# = 0, WR# = 1)
Bit0 : OBF
1 means output buffer is full, 0 means output buffer is empty.
Bit1 : IBF
1 means input buffer is full, 0 means input buffer is empty.
Bit2 : system flag
0 after power on
Bit3 : command/Data
1 means last write is command write. 0 means last write is data write.
Bit4 : keylock status
To represent the inhibition of keyboard. 0 means keyboard is inhibited. 1
means keyboard is not inhibited.
Bit5 : transmit time-
Act as transmit time-out on AT mode. 1 means error happens. Act as Mouse
out/mouse OBF
OBF on PS2 mode. 1 means mouse output buffer full.
Bit6 : receive time-
Act as receive time-out on AT mode. 1 means error happens. Act as general
out/general time-out
(receive/transmit) time-out on PS2 mode.
Bit7 : parity error
1 means even parity has occurred in the last transmit/receive.
Table 2. Command register: read/write (use command 20h/60h)
Bit0 : OBF enable
1 means controller will generate high (interrupt) on P24 when output buffer
has been written.
Bit1 : mouse OBF enable 1 means controller will generate high (interrupt) on P25 when mouse data
comes in output buffer.
Bit2 : system flag
Connect to the status register Bit2.
Bit3 : inhibit override
Write a '1' to this Bit will disable the keyboard inhibit function.
Bit4 : prohibit enabling of Write a '1' to this Bit will disable keyboard interface
keyboard interface
Bit5 : IBM PC keyboard On AT mode, 0 means that the controller will do a IBM keyboard like
type protocol/disable
checking on receiving. On PS2 mode, a '1' disable the mouse interface
mouse interface
Bit6 : PC compatible mode Default is 1, means the scan code translation is on.
Bit7 : reserved.
Table 3. Command List: (with A0 = 1, CS# = 0, RD# = 1, WR# = 0)
20h : read command byte After command execution, OBF = 1 means data is ready on the output
register.
buffer.
60h : write command byte Next byte write to Data port will be written to command byte register.
register.
9xh : write low nibble to
(Port13-Port10).
A1h : controller's version After command execution, OBF = 1 means data is ready on the output
number.
buffer.
A4h : check password
Always return 'F1' on output buffer.
command
A7h : disable mouse
After the command execution, Command byte register bit5 = 1 and P23 = 1
interface
on PS2 mode. No effect on AT mode.
A8h : enable mouse
After the command execution, Command byte register bit5 = 0 and P23 = 0
interface
on PS2 mode. No effect on AT mode.
A9h : mouse interface test. Return 00h if the interface is O.K..
AAh : controller's self test Return 55h if the controller is O.K..
ABh : keyboard interface Return 00h if the interface is O.K..
test.
ADh : disable keyboard
interface.
AEh : enable keyboard
interface.
AFh : return version
-3-
5 Page 
VIA Technologies, Inc.
VT82C42
7. Pin Assignments
PLCC 44-Pin Configuration
RESET XTAL1 NC TEST1
TH_SS XTAL2 TEST0 VCC
P27 P26 P25
CS
TL_EA
RD
A0
WR
NC
SYNC
D0
D1
D2
D3
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P24
P17
P16
P15
P14
NC
P13
P12
P11
P10
TH_SSPP
D4 D5 D6 D7 VSS NC P20 P21 P22 P23 TH_PROG
Fig 9.
DIP 40-Pin Configuration
TEST0
XTAL1
XTAL2
RESET
TH_SS
CS
TL_EA
RD
A0
WR
SYNC
D0
D1
D2
D3
D4
D5
D6
D7
GND
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
Fig 10.
VCC
TEST1
P27
P26
P25
P24
P17
P16
P15
P14
P13
P12
P11
P10
TH_SSPP
TH_PROG
P23
P22
P21
P20
-9-
11 Page | ||
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| PDF Descargar | [ Datasheet VT82C42.PDF ] | |
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