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PDF PCF8549 Data sheet ( Hoja de datos )
| Número de pieza | PCF8549 | |
| Descripción | 65 x 102 pixels matrix LCD driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF8549
65 × 102 pixels matrix LCD driver
Product specification
File under Integrated Circuits, IC12
1997 Nov 21
1 page  
Philips Semiconductors
65 × 102 pixels matrix LCD driver
Product specification
PCF8549
T1, T2, T3, T4, T5, T6 AND T7: TEST PADS
T1, T3, T4, T5, T6 and T7 must be connected to VSS1, T2
is to be left open. Not accessible to user.
SDA/SDA_OUT: I2C DATA LINES
Output and input are separated. If both pads are
connected together they behave like a standard I2C pad.
SCL: I2C CLOCK SIGNAL
Input for the I2C-bus clock signal.
SA0: SLAVE ADDRESS
With the SA0 pin two different slave addresses can be
selected. That allows to connect two PCF8549 LCD
drivers to the same I2C-bus.
OSC: OSCILLATOR
When the on-chip oscillator is used this input must be
connected to VDD1. An external clock signal, if used, is
connected to this input.
FUNCTIONAL DESCRIPTION
Block diagram functions
OSCILLATOR
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to VDD1. An external
clock signal, if used, is connected to this input.
I2C INTERFACE
The I2C interface receives and executes the commands
sent via the I2C-bus. It also receives RAM-data and sends
them to the RAM. During read access the 8-bit parallel
data or the status register content is converted to a serial
data stream and output via the I2C-bus.
DISPLAY CONTROL LOGIC
The display control logic generates the control signals to
read out the RAM via the 101 bit parallel port. It also
generates the control signals for the row, and
column drivers.
RES: RESET
This signal will reset the device. Signal is active low.
DISPLAY DATA RAM (DDRAM)
The PCF8549 contains a 65 × 102 bit static RAM which
stores the display data. The RAM is divided into 8 banks of
102 bytes and one bank of 102 bits
((8 × 8 + 1) × 102 bits). During RAM access, data is
transferred to the RAM via the I2C interface. There is a
direct correspondence between X-address and column
output number.
TIMING GENERATOR
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the I2C-bus.
LCD ROW AND COLUMN DRIVERS
The PCF8549 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages to the
display in accordance with the data to be displayed.
Figure 2 shows typical waveforms. Unused outputs should
be left unconnected.
1997 Nov 21
5
5 Page 
Philips Semiconductors
65 × 102 pixels matrix LCD driver
Product specification
PCF8549
RAM access
If the D/C bit is 1 the RAM can be accessed in both read
and write access mode, depending on the R/W bit. The
data is written to the RAM during the acknowledge cycle.
Set Address
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal.
START AND STOP CONDITIONS (see Fig.10)
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is
HIGH is defined as the STOP condition (P).
Set Read
Modify Write Mode
Read Data
Write Data
no
Finished?
yes
END
Fig.8 Read modify write access.
I2C-BUS INTERFACE
Characteristics of the I2C-bus
The I2C-bus is for bi-directional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
BIT TRANSFER (see Fig.9)
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
SYSTEM CONFIGURATION (see Fig.11)
• Transmitter: The device which sends the data to the bus
• Receiver: The device which receives the data from the
bus
• Master: The device which initiates a transfer, generates
clock signals and terminates a transfer
• Slave: The device addressed by a master
• Multi-Master: More than one master can attempt to
control the bus at the same time without corrupting the
message
• Arbitration: Procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronisation: Procedure to synchronize the clock
signals of two or more devices.
ACKNOWLEDGE (see Fig.12)
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH signal put on the bus by
the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The
device that acknowledges must pull-down the SDA line
during the acknowledge clock pulse, so that the SDA line
is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken
into consideration). A master receiver must signal an end
of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a stop
condition.
1997 Nov 21
11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet PCF8549.PDF ] | |
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