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PDF UPD6708CX Data sheet ( Hoja de datos )
| Número de pieza | UPD6708CX | |
| Descripción | IEBusa Inter Equipment Busa PROTOCOL CONTROL LSI | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6708
IEBus™ (Inter Equipment Bus™) PROTOCOL CONTROL LSI
DESCRIPTION
The µPD6708 is a peripheral LSI for microcontrollers that controls the protocol of the IEBus.
This LSI processes the protocol of the IEBus. Because it is provided with a transmit/receive buffer, the microcontroller
can concentrate on the application processing of the IEBus. Because the µPD6708 also contains an IEBus driver/receiver,
it can be directly connected to the bus.
FEATURES
• Protocol control of IEBus
• Multi-master system
• Broadcast communication function (commu-
nication between one unit and multiple units)
• Choice of three modes with different trans-
mission speeds
Mode 0
Mode 1
Mode 2
At 12 MHz
Approx. 3.9 Kbps
Approx. 17 Kbps
Approx. 26 Kbps
At 12.58 MHz
Approx. 4.1 Kbps
Approx. 18 Kbps
Approx. 27 Kbps
• On-chip IEBus driver/receiver
• Transmit/receive buffer
Transmit: 4-byte FIFO
Receive: 20-byte FIFO
• Interface with microcontroller
• Three-line serial I/O (SCK, SO, SI pins)
• Transfer with MSB first
• Oscillation frequency (fX): 12 MHz, 12.58 MHz
• In modes 0 and 1: ±1.5 %
• In mode 2:
±0.5 %
• Supply voltage: VDD = 5 V ±10 %
ORDERING INFORMATION
Part Number
Package
µPD6708CX
µPD6708GS
16-pin plastic DIP (300 mil)
16-pin plastic SOP (300 mil)
APPLICATION FIELD
Fields where a small-scale digital data transfer system is required between equipment, such as automobile electronic
systems and industrial equipment
The information in this document is subject to change without notice.
Document No. U10680EJ2V0DS00 (2nd edition)
(Previous No. IC-3282)
Date Published January 1996 P
Printed in Japan
The mark 5 shows major revised points.
© 1993
1 page  
µPD6708
1. PIN FUNCTIONS
1.1 List of Pin Functions
Pin No. Pin Name
1 SCK
2 SI
3 SO
4 IRQ
5 R/W
6 XI
7 XO
8 GND
9 BUS–
10 BUS+
11 AVDD
12 C/D
13 CS
14 RESET
15 TEST
16 VDD
Input/Output
Input
Input
Output
Output
Input
––
––
Input/output
––
Input
Input
Input
Input
––
Function
I/O Format At Reset
Input for serial clock used to interface with microcontroller. CMOS input Input
Input for serial data used to interface with microcontroller. CMOS input Input
Output for serial data used to interface with microcontroller. CMOS output High level
Output used by interrupt request signals generated by
communication and command execution results.
Used as operation start request signal to microcontroller.
The interrupt request signal is output for 8 µs or longer
at high level.
CMOS output Low level
Input for switching serial interface read/write mode.
When high, it is in the read mode. When low, it is in the
write mode.
When this pin is low and C/D pin high, the read and write
modes can be switched by commands input from the serial
interface.
CMOS input
Input
Connection pins for system clock resonator.
Use a 12- or 12.58-MHz crystal, or ceramic resonator.
Frequency precision depends on the communication mode
used.
Mode 0 : ±1.5 %
Mode 1 : ±1.5 %
Mode 2 : ±0.5 %
––
(Oscillation
continues)
Ground
–– ––
Input/output for IEBus.
–– High
impedance
IEBus driver/receiver analog power supply. Connect to VDD. ––
––
Input used to switch between processing data input to the
serial interface as commands or data.
When set to high, data is processed as commands; when
low, data is processed as data.
When this pin is high and R/W pin low, the read and write
modes can be switched by commands input from the serial
interface.
CMOS input
Input
Chip select input.
When low, serial interface input is enabled.
When high, serial clock (SCK) input is disabled, SO pin
becomes high impedance, and the serial clock counter is
reset.
The status of CS pin is not affected by IEBus transmit and
receive operations.
CMOS input
Input
System reset signal input pin.
Low input effects a reset.
Always input the low signal for 6 µs or longer after turning
on the power.
CMOS input
Input
Always connect this pin to the VDD.
CMOS input ––
Positive power supply input. Apply a voltage of 5 V ±10 %. ––
––
5
5 Page 
µPD6708
(2) Master address field
The master address field is used to transmit the unit address of the master unit (master address) to the other units.
The master address field consists of master address bits and a parity bit.
The master address comprises 12 bits and is output from the MSB.
If two or more units start transmitting the broadcast bit of the same value simultaneously, the arbitration decision is made
by the master address field.
The master address field compares the data the master has output with the data on the bus each time the master transmits
1 bit of data. If the master address output by the master unit is different from the data on the bus, the master unit assumes
that it has lost in arbitration, stops transmission, and enters the reception state.
Because the IEBus has a wired-AND configuration, the unit having the lowest master address of the units participating
in the arbitration (arbitration masters) wins in the arbitration. Ultimately, only one unit remains in the transmission state
as the master unit after outputting a 12-bit master address.
This master unit then outputs a parity bit ,Note makes the other units confirm the master address, and then outputs the
slave address field.
5
Note Even parity is used. When the number of the bits that are ‘1’ in the master address is odd, the parity bit is ‘1’.
(3) Slave address field
The slave address field is used to transmit the address (slave address) of a unit (slave unit) with which the master wishes
to communicate.
The slave address field consists of slave address bits, a parity bit, and an acknowledge bit.
The slave address comprises 12 bits and is output from the MSB. After the 12-bit slave address is transmitted, the parity
bit is output to prevent the slave address from being received incorrectly. Next, the master unit looks for the acknowledge
signal (bit) from the slave unit to confirm that the slave unit exists on the bus. When the master unit detects the acknowledge
signal, it starts outputting the control field. In the case of broadcast communication, however, the master unit outputs the
control field without waiting for the acknowledge bit.
A slave unit outputs the acknowledge signal if it has detected that its slave address coincides with that selected by the
master and that the parities of both the master and slave addresses are even. If the parity is odd, the slave unit assumes
that the master or slave address has not been correctly received, and does not output the acknowledge signal. In this case,
the master unit enters the standby (monitor) state and communication ceases.
In the case of broadcast communication, the slave address is used to distinguish between group broadcast and general
broadcast as follows:
Slave address = FFFH: General broadcast communication
Slave address ≠ FFFH: Group broadcast communication
Remark In the case of group broadcast communication, the group number is the value of higher 4 bits of the slave
address.
11
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