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PDF UPD178024 Data sheet ( Hoja de datos )
| Número de pieza | UPD178024 | |
| Descripción | 8-BIT SINGLE-CHIP MICROCONTROLLER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD178023,178024
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178023, 178024 are 8-bit single-chip CMOS microcontrollers containing hardware for digital tuning
systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit.
In addition, three serial interfaces, I2C bus (IIC0), three-wire (SIO3), and UART are provided.
Moreover, a flash memory model, the µPD178F124, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User’s Manuals:
µPD178024, 178124 Subseries User’s Manual : U13915E
78K/0 Series User’s Manual - Instruction : U12326E
FEATURES
• High-capacity ROM and RAM
Item Program Memory (ROM)
Part Number
µPD178023
24K bytes
µPD178024
32K bytes
Data Memory
Internal high-speed RAM
1024 bytes
• Instruction cycle:
0.45/0.89/1.78/3.56/7.11 µs (with crystal resonator of
fX = 4.5 MHz)
• Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (I2C bus and UART mode), timers, frequency
counter, power-ON clear circuit
• Hardware for PLL frequency synthesizer
Dual modulus prescaler, programmable divider,
phase comparator, charge pump
• Vectored interrupt sources: 17
• Supply voltage
:VDD = 4.5 to 5.5 V (during PLL and CPU
operations)
:VDD = 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U14126EJ1V0DS00 (1st edition)
Date Published September 1999 N CP(K)
Printed in Japan
©
1999
1 page  
µPD178023, 178024
Item
Frequency counter
Reset
Supply voltage
Package
µPD178023
µPD178024
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
• Reset by RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit
• Detection of less than 4.5 VNote (Reset does not occur, however.)
• Detection of less than 3.5 VNote (during CPU operation)
• Detection of less than 2.3 VNote (in STOP mode)
• VDD = 4.5 to 5.5 V (during CPU, PLL operation)
• VDD = 3.5 to 5.5 V (during CPU operation)
• 80-pin plastic QFP (14 × 20 mm, 0.8-mm pitch)
• 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
(2/2)
Note These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
Data Sheet U14126EJ1V0DS00
5
5 Page 
µPD178023, 178024
1. PIN FUNCTION LIST
1.1 Port Pins
Pin Name
I/O
P00-P04
I/O
P05, P06
P10-P15
Input
P30-P32
P33
P34
P35
P36
P37
P40-47
I/O
I/O
P50-P57
I/O
P60-P67
I/O
P70
P71
P72
P73
P74
P75
P76
P77
P120-P125
I/O
I/O
P130
P131
P132
Output
Function
Port 0.
7-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 1.
6-bit input port.
Port 3.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 4.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Internal pull-up resistors can be specified in software.
Interrupt function by key input is provided.
Port 5.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 6.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 7.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 12.
6-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 13.
3-bit output port.
N-ch open-drain output port (12 V withstand)
At Reset
Input
Shared by:
INTP0-INTP4
Input
—
ANI0-ANI5
Input
Input
—
TI50
TI51
—
BEEP0
—
—
Input
—
Input
—
Input
Input
SI3
SO3
SCK3
—
RXD0
TXD0
SDA0
SCL0
—
Low-level
output
TO50
TO51
—
Data Sheet U14126EJ1V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD178024.PDF ] | |
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