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PDF UPD16879 Data sheet ( Hoja de datos )
| Número de pieza | UPD16879 | |
| Descripción | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16879
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
The µPD16879 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOSFET output
circuit. Because it uses MOSFETs in its output stage, this driver IC consumes less power than conventional driver
ICs that use bipolar transistors.
Because the µPD16879 controls a motor by inputting serial data, its package has been shrunk and the number of
pins reduced. As a result, the performance of the application set can be improved and the size of the set has been
reduced.
This IC employs a current-controlled 64-step micro step driving method that drives stepper motor with low
vibration.
The µPD16879 is a housed in a 38-pin shrink SOP to contribute to the miniaturization of application set.
This IC can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
FEATURES
• Four H bridge circuits employing power MOS FETs
• Current-controlled 64-step micro step driving
• Motor control by serial data (8 bits × 13 bytes)
PWM-frequency, output current and number of output pulse can be setting by serial data.
• 3-V power supply.
Minimum operating voltage: 2.7 V
• Low consumption current.
VDD pin current (operating mode) : 3 mA (MAX.)
• Power save circuit bult in.
VDD pin current (power save mode) : 100 µA (MAX.) fCLK: OFF state
VDD pin current (power save mode) : 300 µA (MAX.) fCLK: 4.5 MHz input
• 38-pin shrink SOP (7.62 mm (300))
ORDERING INFORMATION
Part Number
Package
µPD16879GS-BGG
38-pin plastic shrink SOP (7.62 mm (300))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14188EJ1V0DS00 (1st edition)
Date Published July 2000 N CP(K)
Printed in Japan
©
2000
1 page  
µPD16879
Table 2. Relation Between Rotation Angle, Phase Current, and Vector Quantity
(64-DIVISION MICRO STEP)
(Value of µPD16879 for reference)
STEP
Rotation angle (θ)
A phase current
B phase current
Vector quantity
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
TYP.
θ0
0
− 0 − − 100 −
100
θ1
5.6
2.5 9.8 17.0 − 100 −
100.48
θ2
11.3
12.4
19.5
26.5
93.2
98.1
103
100
θ3
16.9
22.1
29.1
36.1
90.7
95.7 100.7
100.02
θ4
22.5
31.3
38.3
45.3
87.4
92.4
97.4
100.02
θ5
28.1
40.1
47.1
54.1
83.2
88.2
93.2
99.99
θ6
33.8
48.6
55.6
62.6
78.1
83.1
88.1
99.98
θ7
39.4
58.4
63.4
68.4
72.3
77.3
82.3
99.97
θ8
45
65.7
70.7
75.7
65.7
70.7
75.7
99.98
θ9
50.6
72.3
77.3
82.3
58.4
63.4
68.4
99.97
θ 10
56.3
78.1
83.1
88.1
48.6
55.6
62.6
99.98
θ 11
61.9
83.2
88.2
93.2
40.1
47.1
54.1
99.99
θ 12
67.5
87.4
92.4
97.4
31.3
38.3
45.3
100.02
θ 13
73.1
90.7
95.7
100.7
22.1
29.1
36.1
100.02
θ 14 78.8 93.2 98.1 103 12.4 19.5 26.5 100
θ 15 84.4
− 100 − 2.5 9.8 17.0
100.48
θ 16 90
− 100 − − 0 −
100
Remark These data do not indicate guaranteed values.
Data Sheet S14188EJ1V0DS00
5
5 Page 
RESET
VD
VD
LATCH
Initialization
S1 S2
S3
S4 pulse 0
S5 PS
S6 PS
S7 release PS S8
S9 Enable S10 release PS S11
S12 data error S13 normal data S14
DATA
SCLK
OSCOUT
Start point wait
(FF1)
Start point wait+
Start point magnetize wait
(FF2)
ENABLE OUTNote 1
CHOPPING
EXP 0, 1
PULSE OUT
PULSE GATE
(FF3)
PULSE CHECKNote 2
(FF7)
CHECK SUMNote 3
S1 S2 S3 S4
S2 S3 S4 S4
H level fixation
It reverts from the VD
start after a PS release.
L level fixation
S7
S8
S8
S9
S9
S10
S10
S11
S11
S12
S12
S13
S13
S14
L level fixation
Start from
Stop from LATCH ↓
LATCH ↓
EXP can be change in PS period too.
S2 S3 S4
Pulse is nothing
because pulse
data is "0"
S5 to S7
Pulse is nothing
because PS data
Pulse count is done
in enable period too
S8 S9 S10
S11
Pulse is nothing
because
error data.
S13
Output L level
because
error data
SCLK
SDATA
1st byte → 13th byte
D0 D1 D2 D3 D4 D5 D6 D7
(LSB)
Data is held at rising edge SCLK
Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from
low to high, and at the falling edge of FF2 when the level changes from
high to low.
2. FF7 is an output signal that is used to check for the presence or
absence of a pulse in the serial data, is updated at the falling edge of
LATCH and reset once at the rising edge of LATCH. If CHECK SUM
is other than "00h", FF7 goes low, inhibiting pulse output, even if a
pulse is generated.
3. CHECK SUM output is updated at the falling edge of LATCH.
11 Page | ||
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| PDF Descargar | [ Datasheet UPD16879.PDF ] | |
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