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PDF UPD16434G-001-12 Data sheet ( Hoja de datos )
| Número de pieza | UPD16434G-001-12 | |
| Descripción | 1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16434
1/8, 1/16 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
µ PD16434 is LCD controller/driver containing the interfacing features for a dot-matrix mode 8-, 16-time division
LCD and a microprocessor. µ PD16434 contains a 5- by 7-dot matrix character generator corresponding to
ASCII/JIS. Therefore, user original patterns can be easily displayed.
FEATURES
• DOT matrix LCD controller/driver
• 8- or 16-time division drive possible with a single chip
8-time-division : 400 (50 by 8) dots
16-time-division : 672 (42 by 16) dots
• 8- or 16-time division drive possible with no chip
8-time-division : n × 400 (50 by 8) dots
16-time-division : n × 800 (50 by 16) dots
• Display data storage RAM : 20 × 50 × 8 bits
• Programmer specified dot (graphic) display
• Capable of alphanumeric and symbolic displays thorough built-in ROM (5 by 7 dots)
160 characters
• Parallel data input/output (Switch able between 4 and 8 bits)
• Cursor manipulation command
• Upgraded version of µ PD7228, µ PD7228A, µ PD7229, µ PD7229A
ORDERING INFORMATION
Part Number
Package
µ PD16434G-xxx-12
80-PIN PLASTIC QFP (14 × 20)
µ PD16434G-001-12
80-PIN PLASTIC QFP (14 × 20), Standard ROM code
5
µ PD16434GF-xxx-3B9
80-PIN PLASTIC QFP (14 × 20)Note
5 µ PD16434GF-001-3B9 80-PIN PLASTIC QFP (14 × 20), Standard ROM code Note
Note This package is only available in European market.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S10299EJ4V0DS00 (4th edition)
Date Published April 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
1994, 1999
1 page  
µ PD16434
7.2 Stopping Clock Supply and Retaining Data at Low Voltage in Standby Mode ………………………. 36
8. RESET OPERATION …………………………………………………………………………………….. 38
9. COMMANDS ……………………………………………………………………………………………… 40
9.1 LCD Display Mode Setting Commands ……………………………………………………………………... 40
9.2 Data Pointer Load Command …………………………………………………………………………………. 42
9.3 Data Processing Mode Setting Commands ………………………………………………………………… 42
9.4 Memory Bit Manipulation Commands ……………………………………………………………………….. 45
9.5 Standby Operation Setting Command ………………………………………………………………………. 47
10. SYSTEM CONFIGURATION EXAMPLE …………………………………………………………….. 48
11. ELECTRICAL SPECIFICATION ………………………………………………………………………. 49
12. PACKAGE DRAWINGS ………………………………………………………………………………... 60
13. RECOMMENDED SOLDERING CONDITIONS …………………………………………………….. 62
Data Sheet S10299EJ4V0DS00
5
5 Page 
µ PD16434
If the C, /D input indicates command specifications, the data input from the CPU to the serial/parallel interface is
sent from the serial/parallel register to the command decoder for decoding.
In the write mode, if the C, /D input indicates data specifications, the data loaded to the serial/parallel register is
directly transferred to the data memory.
In the AND or OR mode, the data loaded into the serial/parallel register is ANDed or ORed with the data memory
contents, and the result is transferred to the data memory. In the character mode, the data loaded into the
serial/parallel register is regarded as ASCII or JIS code and is sent to the character generator. It is decoded to 5 ×
7-bit character display pattern, and is stored into 5 successive data memory addresses.
Only when set to the read mode, can the serial/parallel interface output data to the CPU. When set to the read
mode, the serial/parallel interface always reads 8-bit data from the data memory and sets it in the serial/parallel register
for the next read operation.
In the serial interface mode, the data in the serial/parallel register is output from the SO pin with the MSB first at
each /SCK falling edge.
In the parallel interface mode, the upper 4 bits of the data in the serial/parallel register are output from the D3 to
D0 pins at the first falling edge of the /STB, and the lower 4 bits of the data in the serial/parallel register are output from
those pins at the second falling edge of the /STB.
In either the serial/parallel interface mode, each time 8 bits of data are output, the next 8 bits of data are
automatically read out from the data memory and set in the serial/parallel register.
2.2 Command Decoder
If the 8-bit data, input through the serial/parallel interface, is specified as a command (C, /D = 1), the data is
clocked in as a command, and is decoded to generate an internal control signal.
2.3 Character Generator
The character generator becomes effective, when a character mode setting command (SCML, SCMR) is
executed. In this case, 8-bit data written through the serial/parallel interface is interpreted as a character code, and the
5 × 7-dot matrix pattern, corresponding to the code, will be generated. It is transferred to the 5 successive addresses in
the data memory (7 bits × 5 times).
The character generator contains the following 160 different pattern data :
ASCII
Upper-case alphabets 26
Lower-case alphabets 26
Numerical characters 10
Symbols
34
JIS
KATAKANA 55
Symbols
9
Figure 2–2 shows correspondence of character codes (ASCII/JIS) and 5 dots × 7 dots display patterns. 96 codes
of 20H to 7FH correspond to ASCII characters, and A0H to DFH correspond to JIS characters.
Data Sheet S10299EJ4V0DS00
11
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