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PDF UPD16430A Data sheet ( Hoja de datos )
| Número de pieza | UPD16430A | |
| Descripción | 1/2/ 1/3/ 1/4 DUTY LCD CONTROLLER/DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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MOS INTEGRATED CIRCUIT
µPD16430A
1/2, 1/3, 1/4 DUTY LCD CONTROLLER/DRIVER
The µPD16430A is an LCD controller/driver that enables the display of LCDs of 1/2 duty, 1/3 duty and 1/4 duty
cycle.
The LCD controller contained in the µPD16430A employs serial data transfer and uses an automatic increment
function for data addresses which eliminates the need to set addresses newly each time.
The LCD driver uses a medium voltage output (14 V max.), which enables higher contrast and a wider viewing angle
even with a 1/3 or 1/4 duty cycle.
By using an on-chip drive bias circuit, it is possible to eliminate the need for external resistors.
FEATURES
• LCD direct drive (medium voltage output: 14 V MAX.)
• Choice of 3 duty cycles
1/2 duty, 1/3 duty, 1/4 duty
• Display dot number:
1/2 duty: 120
1/3 duty: 160
1/4 duty: 240
• 2 types of drive bias
1/2 bias, 1/3 bias
• Choice of 4 types of frame frequency
• Multi-chip configuration possible
• Control through 8-bit serial interface
• On-chip power-on reset circuit
• Low-power dissipation CMOS
• 3.5 to 6.0 V logic supply voltage
ORDERING INFORMATION
Part number
µPD16430AGF-3B9
Package
80-pin plastic QFP (14 × 20)
Document No. IC-2776 (1st edition)
(O.D. No. IC-8302)
Date Published March 1997 N
Printed in Japan
© 1994
1 page  
µPD16430A
No. Symbol
78 BUSY
79 LCDOFF
80 VDD
I/O
Output
Input
—
Output Type
Nch
Open drain
—
—
Description
This pin outputs the serial communication status and the internal data
processing status.
When this signal is a logic high, serial communication is executed.
When this signal is a logic low, it indicates that the display RAM data is
latched to the output buffer.
When the power-on reset circuit is operating, this pin holds a logic low until
a rising or falling signal is input to the STB pin.
This pin serves to turn off all the LCD displays.
When a logic low is input to this pin, all LCD displays are turned off.
Display RAM data is maintained.
Since displays are turned off only by the output driver, serial communica-
tions can be executed as usual.
To turn on displays, it is necessary to input a logic high to this pin and
reset the LCDON flag.
This pin is a power supply pin to the device.
A voltage of 3.5 to 6.0 V is supplied to this pin.
When the supply voltage rises from 0 V to 3 V, or when it reaches a value
under 3 V and then rises again, the power-on reset circuit starts operating
and the device is set to its initialized state.
When the device is in its initialized state, all displays are turned off
(segment and common signals are fixed to VLCD).
Do not supply a voltage higher than VDD to the VLCD pin before the supply
voltage reaches 3.5 V as this will cause incorrect display.
5
5 Page 
(4) Address setting command
MSB
LSB
1 1 0 b4 b3 b2 b1 b0
µPD16430A
Sets RAM group address.
000000 to 001110 (1/2 duty)
000000 to 010011 (1/3 duty)
000000 to 011101 (1/4 duty)
Values at power-on reset
—00 00 0
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet UPD16430A.PDF ] | |
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