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PDF PCF2105MU Data sheet ( Hoja de datos )
| Número de pieza | PCF2105MU | |
| Descripción | LCD controller/driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF2105
LCD controller/driver
Product specification
Supersedes data of 1997 Dec 08
File under Integrated Circuits, IC12
1998 Jul 30
1 page  
Philips Semiconductors
LCD controller/driver
Product specification
PCF2105
6 PINNING
SYMBOL
OSC
VDD
SA0
VSS
R8 to R5
R32 to R29
R24 to R17
C60 to C1
R9 to R16
R25 to R28
R1 to R4
SCL
E
RS
R/W
T1
DB7 to DB0
SDA
VLCD
PAD
1
2
3
4
5 to 8
9 to 12
13 to 20
21 to 80
81 to 88
89 to 92
93 to 96
97
98
99
100
101
102 to 109
110
111
I/O DESCRIPTION
I oscillator/external clock input
− logic supply voltage
I I2C-bus address selection input
− logic ground
O LCD row driver outputs
O LCD row driver outputs
O LCD row driver outputs
O LCD column driver outputs
O LCD row driver outputs
O LCD row driver outputs
O LCD row driver outputs
I I2C-bus serial clock input
I data bus clock input
I register select input
I read/write input
I test input
I/O 8-bit bidirectional data bus input/output
I/O I2C-bus serial data input/output
I LCD supply voltage input
7 PAD FUNCTIONS
7.1 RS: Register Select (parallel control)
Bit RS selects the register to be accessed for read and
write when the device is controlled by the parallel interface.
RS = 0 selects the instruction register for write and the
busy flag and address counter for read. RS = 1 selects the
data register for both read and write. There is an internal
pull-up resistor on pad RS.
7.2 R/W: read/write (parallel control)
R/W selects either the read (R/W = 1) or write (R/W = 0)
operation when control is by the parallel interface. There is
an internal pull-up resistor on pad R/W.
7.3 E: data bus clock (parallel control)
Pad E should be HIGH to signal the start of a read or write
operation when the device is controlled by the parallel
interface. Data is clocked in or out of the chip on the falling
edge of the clock. Note that pad E must be connected to
VSS (logic 0) when I2C-bus control is used.
7.4 DB7 to DB0: data bus (parallel control)
The bidirectional, 3-state data bus transfers data between
the system controller and the PCF2105. DB7 acts as the
busy flag, signalling that internal operations are not yet
completed. In 4-bit operations, DB7 to DB4 are used and
DB3 to DB0 must be left open-circuit. There is an internal
pull-up resistor on each of the data lines. Note that
pads DB7 to DB0 must be left open-circuit when I2C-bus
control is used.
7.5 C60 to C1: column driver outputs
Pads C60 to C1 output the data for pairs of columns.
This arrangement permits optimized Chip-On-Glass
(COG) layout for 4-line by 12 characters.
7.6 R32 to R1: row driver outputs
Pads R32 to R1 output the row select waveforms to the
left and right halves of the display.
7.7 VLCD: LCD power supply
Negative power supply for the liquid crystal display.
1998 Jul 30
5
5 Page 
Philips Semiconductors
LCD controller/driver
Product specification
PCF2105
handbook, full pagewidth
character codes
(DDRAM data)
76 5 43 2 10
higher
order
bits
lower
order
bits
00 0 00 0 00
00 0 00 0 01
00 0 00 0 10
CGRAM
address
6 5 43 2 10
higher
order
bits
lower
order
bits
00 0 00 0 0
001
010
011
100
101
110
111
00 0 10 0 0
001
010
011
100
101
110
111
0 0 1 00 0 0
001
00 0 01 1 11
00 0 01 1 11
00 0 01 1 11
00 0 01 1 11
1111100
1111101
1111110
1111111
character patterns
(CGRAM data)
higher
order
bits
4 3 21 0
lower
order
bits
0
0 00
0 00
0
0 00
00
0
0 00
0 0 00 0
0 00
0 00
00
00
00
00
00
00
0 0 00 0
character
pattern
example 1
cursor
position
character
pattern
example 2
MGA800 - 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the
cursor. Data in the 8th line will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in this figure.
CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data is logic 1 corresponds to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction or
by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address’ instruction.
Fig.6 Relationship between CGRAM addresses, data and display patterns.
1998 Jul 30
11
11 Page | ||
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| PDF Descargar | [ Datasheet PCF2105MU.PDF ] | |
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