UMA1019AM Datasheet PDF - NXP Semiconductors
| Part Number | UMA1019AM | |
| Description | Low-voltage frequency synthesizer for radio telephones | |
| Manufacturers | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
UMA1019AM
Low-voltage frequency synthesizer
for radio telephones
Product specification
Supersedes data of November 1994
File under Integrated Circuits, IC03
1995 Jul 07
|
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Philips Semiconductors
Low-voltage frequency synthesizer
for radio telephones
Product specification
UMA1019AM
FUNCTIONAL DESCRIPTION
General
Programmable reference and main dividers drive the
phase detector. Two charge pumps produce phase error
current pulses for integration in an external loop filter. A
hardwired power-down input POFF (pin 9) ensures that
the dividers and phase comparator circuits can be
disabled.
The RFI input (pin 6) drives a pre-amplifier to provide the
clock to the first divider stage. The pre-amplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from 100 mV up to
500 mV (RMS), and at frequencies as high as 1.7 GHz.
The high frequency divider circuits use bipolar transistors,
slower bits are CMOS. Divider ratios (512 to 131 071)
allow up to 2 MHz phase comparison frequency.
The reference and main divider outputs are connected to
a phase/frequency detector that controls two charge
pumps. The two pumps have a common bias-setting
current that is set by an external resistance. The ratio
between currents in fast and normal operating modes can
be programmed via the 3-wire serial bus. The low current
pump remains active except in power-down. The high
current pump is enabled via the control input FAST (pin 1).
By appropriate connection to the loop filter, dual bandwidth
loops are provided: short time constant during frequency
switching (FAST mode) to speed-up channel changes and
low bandwidth in the settled state (on-frequency) to reduce
noise and breakthrough levels.
The synthesizer speed-up charge pump (CPF) is
controlled by the FAST input in synchronization with phase
detector operation in such a way that potential
disturbances are minimized. The dead zone (caused by
finite time taken to switch the current sources on or off) is
cancelled by feedback from the normal pump output to the
phase detector improving linearity.
An open drain transistor drives the output pin LOCK
(pin 20). It is recommended that the pull-up resistor from
this pin to VDD is chosen to be of sufficient value to keep
the sink current in the LOW state to below 400 µA. The
output will be a current pulse with the duration of the
selected phase error. By appropriate external filtering and
threshold comparison an out-of-lock or an in-lock flag is
generated. The out-of-lock function can be disabled via the
serial bus.
Serial programming bus
A simple 3-line unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and E (enable). The
data sent to the device is loaded in bursts framed by E.
Programming clock edges and their appropriate data bits
are ignored until E goes active LOW. The programmed
information is loaded into the addressed latch when E
returns inactive HIGH. Only the last 21 bits serially clocked
into the device are retained within the programming
register. Additional leading bits are ignored, and no check
is made on the number of clock pulses. The fully static
CMOS design uses virtually no current when the bus is
inactive. It can always capture new programmed data
even during power-down.
However when the synthesizer is powered-on, the
presence of a TCXO signal is required at pin 8 (fXTAL) for
correct programming.
Data format
Data is entered with the most significant bit first. The
leading bits make up the data field, while the trailing four
bits are an address field. The UMA1019AM uses 4 of the
16 available addresses. The data format is shown in
Table 1. The first entered bit is p1, the last bit is p21.
The trailing address bits are decoded on the inactive edge
of E. This produces an internal load pulse to store the data
in one of the addressed latches. To ensure that data is
correctly loaded at first power-up, E should be held LOW
and only taken HIGH after an appropriate register has
been programmed. To avoid erroneous divider ratios, the
pulse is not allowed during data reads by the frequency
dividers. This condition is guaranteed by respecting a
minimum E pulse width after data transfer. The
corresponding relationship between data fields and
addresses is given in Table 2.
Power-down mode
The power-down signal can be either hardware (POFF) or
software (sPOFF). The dividers are on when both POFF
and sPOFF are at logic 0.
When the synthesizer is reactivated after power-down the
main and reference dividers are synchronized to avoid
possibility of random phase errors on power-up.
1995 Jul 07
5
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| Information | Total 16 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ UMA1019AM.PDF Datasheet ] | |
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