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PDF PCD5008H Data sheet ( Hoja de datos )
| Número de pieza | PCD5008H | |
| Descripción | FLEX Pager Decoder | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCD5008
FLEX™ Pager Decoder
Product specification
Supersedes data of 1997 Oct 27
File under Integrated Circuits, IC17
1998 Jun 17
1 page  
Philips Semiconductors
FLEX™ Pager Decoder
Product specification
PCD5008
7 PINNING
SYMBOL PIN
TOUT0
OSCPD
1
2
VDD1
TEST2
XTAL
EXTAL
VSS1
TEST3
TOUT3
LOBAT
EXTS1
EXTS0
VDD2
SYMCLK
S7
S6
TOUT2
S5
S4
S3
S2
S1
S0
RESET
TOUT1
READY
SS
SCK
VSS2
MOSI
MISO
CLKOUT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PAD
I/O COORDINATE
X/Y; note 1
DESCRIPTION
O −1405/1088 3-state test output; note 2
I −1405/816 internal oscillator power-down; connected to VSS when using the
internal oscillator, connected to VDD when using an external source
− −1405/563 supply voltage
I −1405/306 manufacturing test mode input pin; has to be connected to VSS
O −1405/76 76.8 kHz crystal oscillator output
I −1405/−404 76.8 kHz crystal oscillator input or external clock input
− −1405/−648 ground supply
I −1405/−1104 manufacturing test mode input pin; has to be connected to VSS
O −1125/−1400 3-state test output; note 2
I −863/−1400 low battery voltage detect input
I −633/−1400 most significant bit (MSB) of the symbol currently being decoded
I −398/−1400 least significant bit (LSB) of the symbol currently being decoded
− 134/−1400 supply voltage
O 569/−1400 recovered symbol clock output
O 829/−1400 receiver control output port, 3-state
O 1084/−1400 receiver control output port, 3-state
O 1405/−1093 3-state test output; note 2
O 1405/−718 receiver control output port, 3-state
O 1405/−398 receiver control output port, 3-state
O 1405/−93 receiver control output port, 3-state
O 1405/202 receiver control output port, 3-state
O 1405/502 receiver control output port, 3-state
O 1405/812 receiver control output port, 3-state
I 1405/1114 active LOW reset input
O 1051/1400 3-state test output; note 2
O 721/1400 output driven LOW when the PCD5008 is ready for an SPI packet
I 404/1400 slave select input for SPI communications
I 149/1400 serial clock input for SPI communications
− −100/1400 ground supply
I −516/1400 data input for SPI communications
O −789/1400 data output for SPI communications, 3-state
O −1084/1400 38.4 kHz clock output (derived from 76.8 kHz oscillator)
Notes
1. The pad coordinates are given in µm relating to the centre of the chip and are used in case of naked die delivery.
2. These test outputs may be either left unconnected or connected to VSS in the application.
1998 Jun 17
5
5 Page 
Philips Semiconductors
FLEX™ Pager Decoder
Product specification
PCD5008
8.3.5 SPI PACKET FORMAT
SPI data packets consist of an 8-bit ID (byte 3), followed
by 24 bits of information (byte 2 to byte 0). See Table 1,
note that bit 7 of byte 3 is the first bit on the bus.
8.3.6 SPI TIMING
See Fig.8 and Chapter 11 for the timing specifications of
the SPI.
Table 1 Packet bit assignments
BYTE
3
2
1
0
BIT 7
D31
D23
D15
D7
BIT 6
D30
D22
D14
D6
BIT 5
D29
D21
D13
D5
BIT 4
D28
D20
D12
D4
BIT 3
D27
D19
D11
D3
BIT 2
D26
D18
D10
D2
BIT 1
D25
D17
D9
D1
BIT 0
D24
D16
D8
D0
handbook, full pagewidth
SS
READY
tLEAD1
td(SS-READY)
tLEAD2
Tcy(SCK)
tr
tSSH
tREADYH
tLAG2
tf tLAG1
SCK
Zo(off)
MISO
tSCKL
tSCKH
D31
tACC(o)
tDOV
D0
th(o)(D)
to(dis)
MOSI
tsu(i)(D)
D31
th(i)(D)
D0
MBK032
Fig.8 SPI timing.
1998 Jun 17
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCD5008H.PDF ] | |
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