|
|
PDF IDT82V3011PV Data sheet ( Hoja de datos )
| Número de pieza | IDT82V3011PV | |
| Descripción | T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT82V3011PV (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
T1/E1/OC3 WAN PLL WITH
SINGLE REFERENCE INPUT
IDT82V3011
FEATURES
• Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
4 Enhanced and Stratum 4 timing for DS1 interfaces
• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
• Selectable input reference: 8 kHz, 1.544 MHz, 2.048 MHz or 19.44
MHz
• Provides C1.5o, C3o, C2o, C4o, C6o, C8o, C16o, C19o and C32o
output clock signals
• Provides 7 types of 8 kHz framing pulses: F0o, F8o, F16o, F19o,
F32o, RSP and TSP
• Provides a C2/C1.5 output clock signal with the frequency
controlled by the reference input Fref
• Holdover frequency accuracy of 0.025 ppm
• Phase slope of 5 ns per 125 µs
• Attenuates wander from 2.1 Hz
• Fast lock mode
• Provides Time Interval Error (TIE) correction
• MTIE of 600 ns
• JTAG boundary scan
• Holdover status indication
• Freerun status indication
• Normal status indication
• Lock status indication
• Input reference quality indication
• 3.3 V operation with 5 V tolerant I/O
• Package available: 56-pin SSOP
FUNCTIONAL BLOCK DIAGRAM
TDO TDI
OSCi
TCLR
RST VDD VSS VDD VSS VDD VSS VDD VSS
TCK
TMS
TRST
FLOCK
Fref
JTAG
OSC
TIE Control
Block
Virtual
Reference
DPLL
MON_out
Reference
Input Monitor
Invalid Input
Signal
Detection
Feedback Signal
C2/C1.5
C32o
C19o
C19POS
C19NEG
C16o
C8o
C4o
C2o
C3o
C1.5o
C6o
F0o
F8o
F16o
F19o
F32o
RSP
TSP
LOCK
State Control Circuit
Input Frequency
Selection
TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun
F_sel1 F_sel0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc.
1
OCTOBER 22, 2003
DSC-6237/3
1 page  
IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT
INDUSTRIAL TEMPERATURE RANGE
Figure - 1
Figure - 2
Figure - 3
Figure - 4
Figure - 5
Figure - 6
Figure - 7
Figure - 8
Figure - 9
Figure - 10
Figure - 11
Figure - 12
Figure - 13
Figure - 14
LIST OF FIGURES
IDT82V3011 SSOP56 Package Pin Assignment ................................................................................................................................ 2
State Control Circuit ............................................................................................................................................................................ 9
State Control Diagram......................................................................................................................................................................... 9
TIE Control Block Diagram................................................................................................................................................................ 11
Reference Switch with TIE Control Block Enabled............................................................................................................................ 11
Reference Switch with TIE Control Block Disabled........................................................................................................................... 12
DPLL Block Diagram ......................................................................................................................................................................... 12
Clock Oscillator Circuit ...................................................................................................................................................................... 14
Power-Up Reset Circuit..................................................................................................................................................................... 14
Timing Parameter Measurement Voltage Levels .............................................................................................................................. 25
Input to Output Timing (Normal Mode).............................................................................................................................................. 27
Output Timing 1................................................................................................................................................................................. 28
Output Timing 2................................................................................................................................................................................. 29
Input Control Setup and Hold Timing ................................................................................................................................................ 29
5
5 Page 
IDT82V3011 T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT
INDUSTRIAL TEMPERATURE RANGE
2.5 TIE CONTROL BLOCK
If the input reference is badly damaged or lost, it is necessary to use
the reference generated by storage techniques instead. But when
changing the operating mode, a step change in phase on the input
reference will occur. A step change in phase in the DPLL input may lead
to an unacceptable phase change on the output signals. The TIE control
block, when enabled, prevents a step change in phase on the input
reference signal from causing a step change in phase on the output of
the DPLL block. Figure - 4 shows the TIE Control Block diagram.
TIE_en
Step Generation
Fref
Feedback
Signal
Measure
Circuit
Storage
Circuit
Trigger Circuit
Virtual
Reference
Signal
TCLR
Figure - 4 TIE Control Block Diagram
When the TIE Control Block is enabled manually or automatically (by
the TIE_en pin or TIE auto-enable logic generated by the State Control
Circuit), it works under the control of the Step Generation circuit.
At the Measure Circuit stage, the input reference signal (Fref) is
compared with the feedback signal (current output feed back from the
Frequency Select Circuit). The phase difference between the input
reference and the feedback signal is stored in the Storage Circuit for TIE
correction. According to the value stored in the storage circuit, the
Trigger Circuit generates a virtual reference with the same phase as the
previous reference. In this way, the reference can be switched without
generating a step change in phase.
Figure - 5 shows the phase transient that will result if a mode change
is performed with the TIE Control Block enabled.
The value of the phase difference in the Storage Circuit can be
cleared by applying a logic low reset signal to the TCLR pin. The
minimum width of the reset pulse should be 300 ns.
When the IDT82V3011 primarily enters the Holdover mode for a
short time period and then returns back to the Normal mode, the TIE
Control Circuit should not be enabled. This will prevent undesired
accumulated phase change between the input and output.
If the TIE Control Block is disabled manually or automatically, a
mode change will result in a phase alignment between the input signal
and the output signal as shown in Figure - 6. The slope of the phase
adjustment is limited to 5 ns per 125 µs.
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Input Clock
Output Clock
Figure - 5 Reference Switch with TIE Control Block Enabled
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V3011PV.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT82V3011PV | T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT | Integrated Device |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |