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PDF IDT79RC32134 Data sheet ( Hoja de datos )
| Número de pieza | IDT79RC32134 | |
| Descripción | RISCore32300TM Family System Controller Chip | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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RISCore32300TM Family
System Controller Chip
IDT79RC32134
Features
x RC32300-family System Controller
– Direct connection between RC32364 and RC32134
– Up to 75 MHz operation
– Drives latched address bus to memory and peripherals
– Direct control of optional external data buffers
– Programmable system watch-dog timers
– Big or Little endian support
x Interrupt Control
– Provides services for internal and external sources
– Allows status of each interrupt to be read and masked
x Three general purpose 32-bit timer/counters
x Programmable IO (PIO)
– Input/Output/Interrupt source
– Individually programmable
x SDRAM/EDODRAM Controller (32-bit memory only)
– 4 banks, non-interleaved, 256 MB total
– Automatic refresh generation
x UART Interface
– Two 16550 Compatible UARTs
– Baud rate support up to 1.5M
x 8/16/32-bit boot PROM support
x Boundary Scan JTAG Interface (IEEE Std. 1149.1
compatible)
x Memory & Peripheral Controller
– 6 banks, up to 8MB per bank
– 8/16/ or 32-bit interface per bank
– Supports Flash ROM, SRAM, dual-port memory, and periph-
eral devices
– Intel or Motorola style IO supports external wait-state genera-
tion
x 4 DMA Channels
– 4 general purpose DMA, each with Endianness swappers and
byte lane data alignment
– Any channel can be used for PCI
– Supports memory-to-memory, memory-to-I/O,memory-to-
PCI, PCI-to-PCI, I/O-to-I/O transfers, and I/O support of
scatter/gather
– Supports chaining via linked lists of records
– Supports unaligned transfers
– Supports burst transfers
– Programmable burst size
x PCI Bridge
– 32-bit PCI, up to 33 MHz
– Revision 2.1 compliant
– Target and master
– Host or satellite
– Three slot PCI arbiter, on-chip
– Serial EEPROM support, for loading configuration
registers
x 3.3V core operation
x 3.3V I/O operation with 5V tolerant I/O
x 208 pin PQFP package
Block Diagram
Timer, UART,
Interrupt Modules
DMA Channels
RC32134
CPU I/F
PCI I/F and Bridge
EDO/SDRAM
Control
Memory I/O
Control
Data & Address bus
SDRAM/EDODRAM Control
Memory &
I/O Control
PCI Bus
The IDT logo is a registered trademark. RC64145, RC64474, RC64475, RC32134, RC4600, RC4640, RC4650, RC4700, RC3041, RC3051, RC3052, RC3081, RISController, and RISCore are trademarks of Inte-
grated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
1 of 25
April 9, 2001
DSC 5602
1 page  
IDT79RC32134
Pin Description Table
The following table lists the pins provided on the RC32134. Note that several pins are multiplexed and have been assigned alternate functions.
These pins are designated and defined accordingly throughout this table. Also note that those pin names followed by _n are active-low signals.
Pin Name Type Alternate Signal(s)
Description
Local Memory and Peripheral Pins
cpu_ad[31:0]
I/O Not applicable
CPU Address/Data Bus
This is the RC32134’s primary multiplexed and bidirectional address and data bus. The RC32134
latches this bus internally and uses it to generate the necessary address lines to the external memory
and peripherals. If the transaction is a write, the CPU then drives data on cpu_ad(31:0). During CPU
generated transactions, the CPU drives Address(31:4) into the cpu_ad bus, during its address phase.
During DMA generated transactions (or RC32134 internal register reads), the address phase is
unused and the chip drives data during a write.
cpu_addr[3:2]
I Not applicable
CPU LSB Address Bus
During CPU generated transactions, the CPU drives Address(3:2) onto the cpu_addr bus. The
RC32134 does not internally use the cpu_addr bus during the data phase. However, 8- or 16-bit
memory or I/O systems must attach these two pins instead of mem_addr(3:2).
cpu_ale
I Not applicable
CPU Address Latch Enable
During CPU generated transactions, this signal indicates that the cpu_ad (31:0) is driving a valid
address and can be latched internally by the RC32134.
cpu_cip_n
I Not applicable
CPU Cycle In Progress
During CPU generated transactions, this active-low signal indicates that a bus transaction is active.
An external pullup resistor is required.
cpu_wr_n
I Not applicable
CPU Write Status
During CPU generated transactions, this active-low signal indicates whether or not a write is occur-
ring. If a write is not occurring, then the implication is that a read is in progress.
cpu_be_n[3:0]
I Not applicable
CPU Byte Enable Bus
During CPU generated transactions, these active-low signals indicate which byte lanes are in use.
Note: The table below indicates which cpu_be_n signal corresponds to which byte lane, whether or
not the system is in big or little endian mode
cpu_be_n[0]
cpu_be_n[1]
cpu_be_n[2]
cpu_be_n[3]
Data Bits
7:0
15:8
23:16
31:24
cpu_ack_n
cpu_last_n
cpu_buserr_n
O Not applicable
I Not applicable
O Not applicable
CPU Acknowledge
During CPU generated transactions, this active-low signal is generated by the RC32134 to indicate
that the present data have been accepted.
CPU Last Data
During CPU generated transactions, this active-low signal indicates during the data phase that the
present data is the last data.
CPU Bus Error
During both CPU and DMA generated transactions, this active-low signal indicates that a bus error
has occurred. This signal can also be optionally attached to an interrupt line.
Table 2 RC32134 Pin Descriptions (Page 1 of 8)
5 of 25
April 9, 2001
5 Page 
IDT79RC32134
Pin Name Type Alternate Signal(s)
Description
sdram_245_dt_r_n O
DMA Interface
dma_ready_n[1:0]
I/O
dma_done_n[1:0] I/O
Interrupt Controller
interrupt_n
I/O
PIO Interface
pio[11:0]
I/O
Timer/Counter
timer_tc_n[1:0]
timer_gate_n[1:0]
UART Interface
uart_rx[1:0]
uart_tx[1:0]
O
I
I/O
I/O
cpu_dt_r_n
SDRAM FCT245 Direction Transmit/Receive
This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank and is asserted
during DMA read operations. This signal is tri-stated during CPU accesses (when the CPU owns the
bus) and drives during DMA generated accesses.
dma_done_n[1:0]
pio[1:0]
dma_ready_n[1:0]
DMA Ready Negated Bus
Input pin for general purpose DMA channels[1:0] that can initiate the next datum in the current DMA
descriptor frame. dma_ready_n[1:0] pins are not synchronized internally by the RC32134 and thus
must meet the specified setup and hold time with respect to the input clock.
DMA Done
Input pin for general purpose DMA channels[1:0] that can terminate the current DMA descriptor
frame.
cpu_int_n
Interrupt Negated
Uses cpu_int_n. This active-low signal is an interrupt indication to the CPU from RC32134’s Interrupt
Controller.
pci_eeprom_mdo
pci_eeprom_sk
sdram_addr_12
pci_eeprom_mdi
uart _rx[0], uart_tx[0]
uart_rx[1], uart_tx[1]
timer_tc_n[0], timer_tc_n[1]
dma_ready_n[0]
dma_ready_n[1]
Programmable Input/Output
General purpose pins that can each be configured as a general purpose input or general purpose
output.
The pci_eeprom_mdo, pci_eeprom_sk, and sdram_addr12 default to outputs. The rest default to
inputs.
timer_gate_n[1:0], pio[3:2]
timer_tc_n[1:0], pio[3:2]
Timer Terminal Count Overflow Negated
Output indicating that the timer has reached its count compare value and has overflowed back to 0.
Timer Gate Negated
Input indicating that the timer may count one tick on the next clock edge.
pio[7]
pio[5]
pio[6]
pio[4]
UART Receive Data Bus
UART mode: Each UART channel receives data on their respective input pin.
UART Transmit Data Bus
UART mode: Each UART channel sends data on their respective output pin. Note that these pins
default to inputs at reset time and must be programmed via the PIO interface before being used as
UART outputs.
Table 2 RC32134 Pin Descriptions (Page 7 of 8)
11 of 25
April 9, 2001
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet IDT79RC32134.PDF ] | |
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