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Integrated Device - RISC CPU PROCESSOR RISCore

Numéro de référence IDT79R3500
Description RISC CPU PROCESSOR RISCore
Fabricant Integrated Device 
Logo Integrated Device 





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IDT79R3500 fiche technique
IDT79R3500 RISC CPU P®ROCESSOR RISCore
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RISC CPU PROCESSOR
IDT79R3500
RISCore
Integrated Device Technology, Inc.
FEATURES:
• Efficient Pipelining—The CPU’s 5-stage pipeline design
assists in obtaining an execution rate approaching one
instruction per cycle. Pipeline stalls and exceptions are
handled precisely and efficiently.
• On-Chip Cache Control—The IDT79R3500 provides a
high-bandwidth memory interface that handles separate
external Instruction and Data Caches ranging in size from
4 to 256kBs each. Both caches are accessed during a
single CPU cycle. All cache control is on-chip.
• On-Chip Memory Management Unit—A fully-associative,
64-entry Translation Lookaside Buffer (TLB) provides fast
address translation for virtual-to-physical memory map-
ping of the 4GB virtual address space.
• Dynamically able to switch between Big- and Little- Endian
byte ordering conventions.
• Optimizing Compilers are available for C, FORTRAN,
Pascal, COBOL, Ada, PL/1 and C++.
• 20 through 40MHz clock rates yield up to 32VUPS sus-
tained throughput.
• Supports independent multi-word block refill of both the
instruction and data caches with variable block sizes.
• Supports concurrent refill and execution of instructions.
• Partial word stores executed as read-modify-write.
• 6 external interrupt inputs, 2 software interrupts, with
single cycle latency to exception handler routine.
• Flexible multiprocessing support on chip with no impact on
uniprocessor designs.
• A single chip integrating the R3000 CPU and R3010 FPA
execution units, using the R3000A pinout.
• Software compatible with R3000, R2000 CPUs and R3010,
R2010 FPAs.
• TLB disable feature allowing a simple memory model for
Embedded Applications.
• Programmable Tag bus width allowing reduced cost cache.
• Hardware Support of Single- and Double-Precision Float-
ing Point Operations that include Add, Subtract, Multiply,
Divide, Comparisons, and Conversions.
• Sustained Floating Point Performance of 11 MFlops single
precision LINPACK and 7.3MFLOPS double precision
• Supports Full Conformance With IEEE 754-1985 Floating
Point Specification
• 64-bit FP operation using sixteen 64-bit data registers
• Military product compliant to MIL-STD 833, class B
IDT79R3500 PROCESSOR
CONTROL
FPA
Master Pipeline/Bus Control
CPO
(System Control Coprocessor)
CPU
FPA Registers
Exponent Add Unit
FPA Divide Unit
FPA Multiply Unit
Exception/Control
Registers
Memory
Management
Unit Registers
Translation
Lookaside
Buffer
(64 entries)
Local
Control
Logic
Virtual Page Number/
Virtual Address
General Registers
(32x32)
ALU
Shifter
Integer
Multiplier/Divider
Address Adder
PC Increment/Mux
TAG (20+4)
ADDRESS (18)
The IDT logo is a registered trademark and RISCore, CEMOS are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1992 Integrated Device Technology, Inc.
5.3
Data (32+4)
2871 drw 01
OCTOBER 1992
DSC-9054/3

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