IDT79R3081E-25J Datasheet PDF - Integrated Device
| Part Number | IDT79R3081E-25J | |
| Description | RISController with FPA | |
| Manufacturers | Integrated Device | |
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IDT79R3081 RISController
Integrated Device Technology, Inc.
IDT79R3081
RISController™
with FPA
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT 79R3081™ , 79R3081E
IDT 79RV3081, 79RV3081E
FEATURES
• Instruction set compatible with IDT79R3000A, R3041,
R3051, and R3071 RISC CPUs
• High level of integration minimizes system cost
— R3000A Compatible CPU
— R3010A Compatible Floating Point Accelerator
— Optional R3000A compatible MMU
— Large Instruction Cache
— Large Data Cache
— Read/Write Buffers
• 43VUPS at 50MHz
— 13MFlops
• Flexible bus interface allows simple, low cost designs
• Optional 1x or 2x clock input
• 20 through 50MHz operation
• "V" version operates at 3.3V
• 50MHz at 1x clock input and 1/2 bus frequency only
• Large on-chip caches with user configurability
— 16kB Instruction Cache, 4kB Data Cache
— Dynamically configurable to 8kB Instruction Cache,
8kB Data Cache
— Parity protection over data and tag fields
• Low cost 84-pin packaging
• Superset pin- and software-compatible with R3051, R3071
• Multiplexed bus interface with support for low-cost, low-
speed memory systems with a high-speed CPU
• On-chip 4-deep write buffer eliminates memory write stalls
• On-chip 4-deep read buffer supports burst or simple block
reads
• On-chip DMA arbiter
• Hardware-based Cache Coherency Support
• Programmable power reduction mode
• Bus Interface can operate at half-processor frequency
R3081 BLOCK DIAGRAM
BrCond(3:2,0)
ClkIn
Clock Generator
Unit/Clock Doubler
Master Pipeline Control
System Control
Coprocessor
(CP0)
Integer
CPU Core
Exception/Control
Registers
General Registers
(32 x 32)
Memory Management
Registers
ALU
Shifter
Int(5:0)
Translation
Lookaside Buffer
(64 entries)
Mult/Div Unit
Address Adder
PC Control
Virtual Address
FP Interrupt
Floating Point
Coprocessor
(CP1)
Register Unit
(16 x 64)
Exponent Unit
Add Unit
Divide Unit
Multiply Unit
Exception/Control
Physical Address Bus
Data Bus
32 Configurable
Instruction
Cache
(16kB/8kB)
Configurable
Data
Cache
(4kB/8kB)
Data Bus
36
Parity
Generator
4-deep
Read
Buffer
R3051 Superset Bus Interface Unit
4-deep
Write
Buffer
DMA
Arbiter
BIU
Control
Coherency
Logic
Address/
Data
DMA
Ctrl
Rd/Wr
Ctrl
SysClk Invalidate
Control
2889 drw 01
The IDT logo is a registered trademark, and RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400, R4600, IDT/kit, and IDT/sim are trademarks of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
5.5
5.5
SEPTEMBER 1995
DSC-9064/4
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IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
simple handshake signals to process CPU read and write
requests. In addition to the read and write interface, the R3051
family incorporates a DMA arbiter, to allow an external master
to control the external bus.
The R3081 also supports hardware based cache coherency
during DMA writes. The R3081 can invalidate a specified line
of data cache, or in fact can perform burst invalidations during
burst DMA writes.
The R3081 incorporates a 4-deep write buffer to decouple
the speed of the execution engine from the speed of the
memory system. The write buffers capture and FIFO processor
address and data information in store operations, and present
it to the bus interface as write transactions at the rate the
memory system can accommodate.
The R3081 read interface performs both single datum
reads and quad word reads. Single reads work with a simple
handshake, and quad word reads can either utilize the simple
handshake (in lower performance, simple systems) or utilize
a tighter timing mode when the memory system can burst data
at the processor clock rate. Thus, the system designer can
choose to utilize page or nibble mode DRAMs (and possibly
use interleaving, if desired, in high-performance systems), or
use simpler techniques to reduce complexity.
In order to accommodate slower quad word reads, the
R3081 incorporates a 4-deep read buffer FIFO, so that the
external interface can queue up data within the processor
before releasing it to perform a burst fill of the internal caches.
The R3081 is R3051 superset compatible in its bus interface.
Specifically, the R3081 has additional support to simplify the
design of very high frequency systems. This support includes
the ability to run the bus interface at one-half the processor
execution rate, as well as the ability to slow the transitions
between reads and writes to provide extra buffer disable time
for the memory interface. However, it is still possible to design
a system which, with no modification to the PC Board or
software, can accept either an R3041, R3051, R3052, R3071,
or R3081.
SYSTEM USAGE
The IDT R3051 family has been specifically designed to
allow a wide variety of memory systems. Low-cost systems
can use slow speed memories and simple controllers, while
other designers may choose to incorporate higher frequencies,
faster memories, and techniques such as DMA to achieve
maximum performance. The R3081 includes specific support
for high perfromance systems, including signals necessary to
implement external secondary caches, and the ability to
perform hardware based cache coherency in multi-master
systems.
Figure 6 shows a typical system implementation.
Transparent latches are used to de-multiplex the R3081
address and data busses from the A/D bus. The data paths
between the memory system elements and the A/D bus is
managed by simple octal devices. A small set of simple PALs
is used to control the various data path elements, and to
control the handshake between the memory devices and the
CPU.
Depending on the cost vs. performance tradeoffs appropriate
to a given application, the system design engineer could
include true burst support from the DRAM to provide for high-
performance cache miss processing, or utilize a simpler,
lower performance memory system to reduce cost and simplify
the design. Similarly, the system designer could choose to
implement techniques such as external secondary cache, or
DMA, to further improve system performance.
DEVELOPMENT SUPPORT
The IDT R3051 family is supported by a rich set of
development tools, ranging from system simulation tools
through PROM monitor and debug support, applications
software and utility libraries, logic analysis tools, sub-system
modules, and shrink wrap operating systems. The R3081,
which is pin and software compatible with the R3051, can
directly utilize these existing tools to reduce time to market.
Figure 7 is an overview of the system development process
typically used when developing R3051 family applications.
The R3051 family is supported in all phases of project
development. These tools allow timely, parallel development
of hardware and software for R3051 family applications, and
include tools such as:
• Optimizing compilers from MIPS, the acknowledged leader
in optimizing compiler technology.
• Cross development tools, available in a variety of
development environments.
• The IDT Evaluation Board, which includes RAM, EPROM,
I/O, and the IDT PROM Monitor.
• IDT/sim™, which implements a full prom monitor
(diagnostics, remote debug support, peek/poke, etc.).
• IDT/kit™, which implements a run-time support package for
R3051 family systems.
PERFORMANCE OVERVIEW
The R3081 achieves a very high-level of performance. This
performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations in a single cycle, and has
an effective load time of 1.3 cycles, and branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the execution engine
achieves over 35 VUPS performance when operating out
of cache.
• A full featured floating point accelerator/co-processor.
The R3081 incorporates an R3010A compatible floating
point accelerator on-chip, with independent ALUs for floating
point add, multiply, and divide. The floating point unit is fully
hardware interlocked, and features overlapped operation
and precise exceptions. The FPA allows floating point
adds, multiplies, and divides to occur concurrently with
each other, as well as concurrently with integer operations.
• Large on-chip caches. The R3051 family contains caches
which are substantially larger than those on the majority of
today’s microprocessors. These large caches minimize the
number of bus transactions required, and allow the R3051
family to achieve actual sustained performance very close
to its peak execution rate. The R3081 doubles the cache
available on the R3052, making it a suitable engine for
5.5 5
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| Information | Total 38 Pages | |
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