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PDF PC87427 Data sheet ( Hoja de datos )
| Número de pieza | PC87427 | |
| Descripción | ServerI/O with SensorPathTM Health Monitoring | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PC87427 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY
September 2003
Revision 1.0
PC87427
ServerI/O with SensorPathTM Health Monitoring
General Description
The National Semiconductor PC87427 is targeted for a
wide range of servers, workstations and high-end desktops
that use the Low Pin Count (LPC) bus for the host interface
and an SMBus® interface for either a Baseboard Manage-
ment Controller (BMC) or mini-BMC (mBMC), both of which
are optional.
For LPC and SMBus access, the PC87427 features a fast
X-Bus, over which boot flash and I/O devices can be ac-
cessed. The PC87427 supports X-Bus address line forcing
(to 0 or 1) to create memory windows for BIOS data storage.
When VSB exists, the BMC or mBMC can access the
PC87427 and its fast X-Bus via SMBus. The SMBus also
controls serial port float, RTC access, and serial port inter-
connection (snoop and take-over modes). In addition, the
PC87427 provides routing of up to two selected LPC I/O
port transactions to the GPIO Extension Port.
The PC87427 provides a VSB-powered high-frequency clock
for on-chip peripherals; it also provides a configurable high-
frequency clock for other VSB-powered platform components.
The PC87427 supports SensorPath health monitor inter-
face to LMPCxx sensors, fan monitoring and control, and a
chassis intrusion detector.
The System Wake-Up Control (SWC) module supports flex-
ible wake-up and power-off request mechanisms for all plat-
forms (i.e., with or without BMC/mBMC).
The PC87427 supports both I/O and memory mapping of
module registers and enables building legacy-free systems.
The PC87427 also incorporates a Floppy Disk Controller
(FDC), two serial ports (UARTs), a Keyboard and Mouse
Controller (KBC), General-Purpose Input/Output (GPIO),
GPIO extension for additional off-chip GPIO ports, and an
interrupt serializer for parallel IRQs.
Outstanding Features
s Legacy-reduced Advanced I/O, optimized for high-end
platforms. Legacy modules: FDC, two Serial Ports
(UARTs) and a Keyboard and Mouse Controller (KBC).
s SensorPath system health support for LMXX sensors,
fan monitor/control, and chassis intrusion detection, for
all platforms (i.e., with or without a BMC or mBMC).
s 8/16-bit fast X-Bus extension for boot flash, memory
and I/O.
s I/O-mapped and memory-mapped registers.
s VSB-powered SMBus access to modules and fast X-Bus.
s Two sets of BIOS code and data support, for main and
back-up BIOS.
s Extremely low current consumption in Battery Backup
mode.
s Serial Interface for manageability (Serial Interface M).
Two-to-one multiplexing of Serial Ports 1 and 2.
s 52 GPIO ports with a variety of wake-up events, plus
GPIO extension for additional off-chip GPIO ports.
s Watchdog for autonomous system recovery for BIOS
Boot process and for operating system use.
s 128-pin PQFP package.
Block Diagram
Serial
Serial
Serial
Floppy Disk PS/2
KBC Fan Fan Serial LPC
Serial
Interface 1 Interface 2 Interface M Interface Interfaces Ports PWM Tach IRQ Interface Clock Data
ServerI/O
Clock
VDD
Route Matrix
Serial
Port 1
Serial
Port 2
FDC
Keyboard & Fan Monitor LPC Bus
Mouse Controller and Control Interface
SMBus Slave
Interface
VBAT
VSB
System Wake-Up Control
Internal Clocks
RTC
Clock Health Monitor
Generator and Control
Watchdog
GPIO GPIO
Ports Extension
X-Bus
Extension
Wake-Up Power SCI & Chassis 32.768 Low-F High-F SensorPath WDO
Events Control SMI Intrusion KHz Clock Clock Interface
I/O Port XIRQ X-Bus
Ports Extension
Interface
National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. SensorPath is a trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© 2003 National Semiconductor Corporation
www.national.com
1 page  
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM
DIR
FANIN0/P17
DR0/FANOUT3
VSS
VDD
VCORF
MTR0/GPIO37
INDEX/GPIO36
DRATE0/GPIO35
DENSEL/GPIO34
FANIN4/P16
FANIN3
FANIN2
FANOUT0
GPIO57/GPEXD
GPIO56/GPEXC
GPEXC2/FANIN1
LMPCIF/GPIO05/XA10
FANIN5/GPIO26/XA11/VRMTHRM
CHASSIS
GPIO50/DCDM/XCS3
GPIO51/DSRM/XCS2
GPIO52/CTSM/XCS1
HFCKS/DTRM_BOUTM
GPO55/SOUTM/TEST
GPIO54/SINM
GPO53/RTSM/XCNF2
VSB
VSS
DCD1
DSR1
SIN1
RTS1/TRIS
SOUT1
CTS1
XOR_OUT/DTR1_BOUT1/BADDR
RI1
RI2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
PC87427-xxx/VLA
38 GPIOE44/SIOSCI
37 XA6/SIOSMI/GPIO27
36 FANIN6/PWBTIN/XIRQ2
35 GPIOE42/SLBTIN/XIRQ1/SMBALERT
34 XSTB0/XCNF0
33 XSTB1/FANOUT2
32 GPIOE47/SLPS5
31 XA4_XD0/GPIO37
30 XA5_XD1/GPIO36
29 XA6_XD2/GPIO35
28 XA7_XD3/GPIO34
27 XA8_XD4/GPIO33
26 XA9_XD5/GPIO32
25 XA10_XD6/GPIO31
24 XA11_XD7/GPIO30
23 XCS0
22 GPIOE41/XA4/THRMTRIP2
21 GPIOE40/XA5/THRMTRIP1
20 GPIOE46/SLPS3
19 XA0_XA20/GPIO25
18 XA1/GPO24
17 XA2/GPIO23
16 XA3/GPIO22
15 XWR_XRW/GPIO21
14 XRD_XEN/GPIO20
13 GPIO07/HFCKOUT
12 VSB
11 VSS
10 XIRQ0/GPIO06
9 FANIN7/XRDY
8 GPIOE17/XA12_XD8/FANOUT2
7 GPIOE16/XA13_XD9/FANOUT1
6 GPIOE15/XA14_XD10
5 GPIOE14/XA15_XD11
4 GPIOE13/XA16_XD12
3 GPIOE12/XA17_XD13
2 GPIOE11/XA18_XD14
1 GPIOE10/XA19_XD15
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC87427-xxx/VLA
See NS Package Number VLA128A
xxx = Three-character identifier for National data, keyboard ROM and/or customer identification code.
Revision 1.0
5
www.national.com
5 Page 
1.0 Signal/Pin Connection and Description (Continued)
Signal Pin(s) I/O Buffer Type Power Well
Description
DTR1_
100
O
O4/8
BOUT1
DTR2_
BOUT2
108
DTRM_
BOUTM
88
VDD Data Terminal Ready. When low, indicates to the data transfer
device, e.g., modem, that the UART is ready to establish a
communications link. After a system reset, these pins provide the
DTR function and set these signals to inactive high. Loopback
VSB operation holds them inactive.
Baud Output. Provides the associated serial channel baud rate
generator output signal if Test mode is selected, i.e., bit 7 of
EXCR1 register is set.
RI1
101 I INTS
VDD Ring Indicator. When low, indicates that a telephone ring signal
was received by the modem. These pins are monitored during VDD
RI2 102
VSB power-off for wake-up event detection.
RTS1
RTS2
RTSM
97 O
105
91
O3/6
VDD Request to Send. When low, indicates to the modem or other
data transfer device that the corresponding UART is ready to
VSB exchange data. A system reset sets these signals to inactive high,
and loopback operation holds them inactive.
SIN1
SIN2
SINM
96 I
104
90
INTS
VDD Serial Input. Receives composite serial data from the
communications link (peripheral device, modem or other data
VSB transfer device).
SOUT1 98
O O3/6
SOUT2
SOUTM
106
89
VDD Serial Output. Sends composite serial data to the communications
link (peripheral device, modem or other data transfer device).
VSB These signals are set active high after a system reset.
1. DCDM is an output signal due to its role in an exchange connection with an external BMC.
1.4.5 Fan Monitor & Control (FMC)
Signal
FANIN0-7
FANOUT0
FANOUT1
FANOUT2
FANOUT3
Pin(s) I/O Buffer Type Power Well
Description
66, 81,
77, 76,
75, 83,
36, 9
78
7
53
8
33
67
I INTS
O OD12,O6/12
VDD Fan Inputs. Used to feed the fan’s tachometer pulse to the
Fan Speed Monitor.
VDD Fan Outputs. Pulse Width Modulation (PWM) signals, used to
control the speed of cooling fans by controlling the voltage
supplied to the fans motors.
Revision 1.0
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| PDF Descargar | [ Datasheet PC87427.PDF ] | |
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