IDT74FST1632383PV Datasheet PDF - Integrated Device
| Part Number | IDT74FST1632383PV | |
| Description | 20-BIT BUS EXCHANGE SWITCH | |
| Manufacturers | Integrated Device | |
| Logo |  |
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20-BIT BUS EXCHANGE
SWITCH
IDT74FST163383
IDT74FST1632383
ADVANCE INFORMATION
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 5Ω
FST1632xxx — 28Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
DESCRIPTION:
The FST163383/1632383 belong to IDT's family of Bus
switches. Bus switch devices perform the function of connect-
ing or isolating two ports without providing any inherent
current sink or source capability. Thus they generate little or
no noise of their own while providing a low resistance path for
an external driver. These devices connect input and output
ports through an n-channel FET. When the gate-to-source
junction of this FET is adequately forward-biased the device
conducts and the resistance between input and output ports
is small. Without adequate bias on the gate-to-source junction
of the FET, the FET is turned off, therefore with no VCC
applied, the device has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST1632xxx integrates terminating resistors in the
device, thus eliminating the need for external 25Ω series
resistors.
The FST163383 and FST1632383 each provide four 4-bit
TTL- compatible ports that support 2 way bus exchange. The
BX pin controls the bus exchange and the BE pin serves as the
enable pin.
FUNCTIONAL BLOCK DIAGRAM
A0
B0
A4
B4
BX1
BE1
C0 A5
D0 B5
C4 A9
D4 B9
BX2
BE2
C5
D5
C9
D9
3474 drw 01
PIN DESCRIPTION
Pin Names
A0-9, B0-9
I/O
I/O
C0-9, D0-9
BE1,2
I/O
I
BX1,2
I
Description
Buses A, B
Buses C, D
Bus Switch Enable (Active LOW)
Bus Exchange
3474 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
1
MAY 1996
DSC-3474/4
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IDT74FST163383, IDT74FST1632383
20-BIT BUS EXCHANGE SWITCH
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
VIN
Pulse
Generator
D.U.T.
RT
V OUT
50pF
CL
500Ω
500Ω
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
3474 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
3474 lnk 03
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
tSU tH
3V
1.5V
0V
3V
LOW-HIGH-LOW
PULSE
1.5V
INPUT
ASYNCHRONOUS CONTROL
PRESET
tREM
1.5V
0V
3V
tW
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
tH
3V
1.5V
0V
3474 lnk 05
ETC.
3474 lnk 04
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
3474 lnk 06
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
tPLZ
0V
3.5V
3.5V
1.5V
tPHZ
0.3V VOL
1.5V
0.3V VOH
0V 0V
NOTES:
3474 lnk 07
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5
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| Information | Total 6 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT74FST1632383PV.PDF Datasheet ] | |
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