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PDF IDT74FST163232PV Data sheet ( Hoja de datos )
| Número de pieza | IDT74FST163232PV | |
| Descripción | 16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH | |
| Fabricantes | Integrated Device | |
| Logotipo |  |
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16-BIT SYNCHRONOUS
2:1 MUX/DEMUX SWITCH
IDT74FST163232
ADVANCE INFORMATION
Integrated Device Technology, Inc.
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 4Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
DESCRIPTION:
The FST163232 belong to IDT's family of Bus switches.
Bus switch devices perform the function of connecting or
isolating two ports without providing any inherent current sink
or source capability. Thus they generate little or no noise of
their own while providing a low resistance path for an external
driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this
FET is adequately forward-biased the device conducts and
the resistance between input and output ports is small. With-
out adequate bias on the gate-to-source junction of the FET,
the FET is turned off, therefore with no VCC applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST163232 provides three 16-bit TTL- compatible
ports that support 2:1 multiplexing. The S0,1 pins control mux
select and switch enable/disable. The S0,1 inputs are syn-
chronous and clocked on the rising edge of CLK when CLKEN
is low.
Port A can be connected to port B1 or port B2 or both ports
B1 and B2.
FUNCTIONAL BLOCK DIAGRAM
CLKEN
CLK
S0
D
CE
CLK
S1 D
CE
CLK
1A
PIN DESCRIPTION
Pin Names
A
B1, B2
S0,1
CLK
CLKEN
I/O Description
I/O Bus A
I/O Buses B1, B2
I Control Pins
I Clock Input. Clocks S0,1 on
Rising Edge
I Clock Enable Input
3511 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
1
1 of 16 Channels
1B1
1B2
3511 drw 01
FEBRUARY 1997
DSC-3511/2
1 page  
IDT74FST163232
16-BIT SYNCHRONOUS 2:1 MUX/DEMUX SWITCH
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
VIN
Pulse
Generator
D.U.T.
RT
V OUT
50pF
CL
500Ω
500Ω
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
3511 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
3511 lnk 03
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
tSU tH
3V
1.5V
0V
3V
LOW-HIGH-LOW
PULSE
1.5V
INPUT
ASYNCHRONOUS CONTROL
PRESET
tREM
1.5V
0V
3V
tW
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
tH
3V
1.5V
0V
3511 lnk 05
ETC.
3511 lnk 04
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
3511 lnk 06
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
DISABLE
tPLZ
3.5V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
NOTES:
3511 lnk 07
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74FST163232PV.PDF ] | |
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