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PDF PC87365 Data sheet ( Hoja de datos )

Número de pieza PC87365
Descripción 128-Pin LPC SuperI/O with System Hardware Monitoring
Fabricantes National Semiconductor　
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No Preview Available ! PC87365 Hoja de datos, Descripción, Manual

PRELIMINARY
November 2000
Revision 2.01
PC87365
128-Pin LPC SuperI/O with System Hardware Monitoring
General Description
The PC87365, a member of National Semiconductor’s 128-
pin LPC SuperI/O family, features National’s new System
Hardware Monitoring capability. The PC87365 is PC99 and
ACPI compliant, and offers a single-chip solution to the most
commonly used PC I/O peripherals.
System Hardware Monitoring provides minimum power con-
sumption and maximum operating efficiency within the system
environment. It integrates National’s Voltage Level Monitor
(VLM) which monitors system voltages using 8-bit Analog to
Digital (A/D) conversion, seven analog input channels and
VREF input, and National’s diode input Temperature Sensor
for full, PC system thermal control.
The PC87365 also incorporates: Fan Speed Control and
Monitor (FSCM) for three fans, extended wake-up support
for a wide range of wake-up events, system design protection
features, a Floppy Disk Controller (FDC), a Keyboard and
Mouse Controller (KBC), ACCESS.bus® Interface (ACB),
System Wake-Up Control (SWC), General-Purpose In-
put/Output (GPIO) support for 40 ports, Interrupt Serializer
for Parallel IRQs, an enhanced WATCHDOG Timer (WDT),
a full IEEE 1284 Parallel Port and two enhanced Serial Ports
(UARTs), one with Infrared (IR) support.
Outstanding Features
q System Hardware Monitoring including:
— Diode-based Temperature Sensor (TMS)
— Voltage Level Monitor (VLM) with VID inputs
q Extended Wake-Up support, including legacy/ACPI
power button support, direct power supply control in
response to wake-up events, power-fail recovery
q Protection features, including I/O access lock, chassis
hood lock/unlock, chassis intrusion detection, GPIO lock
and pin configuration lock
q Fan Speed Control and Monitor for three fans
q Serial IRQ support (15 options)
q Interrupt Serializer (11 Parallel IRQs to Serial IRQ)
q Bus interface, based on Intel’s LPC Interface Specifi-
cation Revision 1.0, September 29th, 1997
q ACCESS.bus Interface, SMbus® physical layer compatible
q 40 GPIO Ports (29 standard, including 15 with Assert
IRQ/SMI/PWUREQs interrupts; 11 VSB powered)
q Blinking LEDs
q 128-pin PQFP Package
Block Diagram
Serial
Serial Infrared
Interface Interface Interface
I/O
Ports
Floppy Drive Parallel Port LPC Serial Analog
Diode
Interface
Interface Interface IRQ SMI Inputs VREF Interface
Serial Port 1
Serial Port 2
with IR
GPIO Ports
Floppy Disk IEEE 1284
Controller Parallel Port
Bus
Interface
System
Hardware
Monitoring
AV DD
VDD
VBdAT
VSB
System Wake-Up ACCESS.bus
Control
Interface
Power Wake-Up PWUREQ SCL SDA
Control Events
WATCHDOG
Fan Speed
Keyboard &
Timer
Control & Monitor Mouse Controller
WDO
3 Control 3 Monitor Keyboard & Ports
Outputs Inputs Mouse I/F
Interrupt
Serializer
Parallel
IRQs
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© 2000 National Semiconductor Corporation
www.national.com

1 page




PC87365 pdf
Table of Contents
Datasheet Revision Record ................................................................................................................... 4
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM ......................................................................................................... 14
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 15
1.3 PIN MULTIPLEXING ................................................................................................................. 19
1.4 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 21
1.4.1 ACCESS.bus Interface (ACB) .................................................................................... 21
1.4.2 Bus Interface ............................................................................................................... 21
1.4.3 Clock ............................................................................................................................ 21
1.4.4 Fan Speed Control and Monitor (FSCM) ..................................................................... 21
1.4.5 Floppy Disk Controller (FDC) ...................................................................................... 22
1.4.6 General-Purpose Input/Output (GPIO) Ports ............................................................... 23
1.4.7 Infrared (IR) ................................................................................................................. 23
1.4.8 Keyboard and Mouse Controller (KBC) ..................................................................... 24
1.4.9 Parallel Port ............................................................................................................... 24
1.4.10 Power and Ground ..................................................................................................... 25
1.4.11 Protection .................................................................................................................... 26
1.4.12 Serial Port 1 and Serial Port 2 ..................................................................................... 26
1.4.13 Strap Configuration ...................................................................................................... 27
1.4.14 System Hardware Monitoring ...................................................................................... 27
1.4.15 System Wake-Up Control ............................................................................................ 28
1.4.16 WATCHDOG Timer (WDT) ......................................................................................... 28
1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 29
2.0 Device Architecture and Configuration
2.1 OVERVIEW ............................................................................................................................... 31
2.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 31
2.2.1 The Index-Data Register Pair ...................................................................................... 31
2.2.2 Banked Logical Device Registers Structure ................................................................ 33
2.2.3 Standard Logical Device Configuration Register Definitions ....................................... 34
2.2.4 Standard Configuration Registers ............................................................................... 36
2.2.5 Default Configuration Setup ........................................................................................ 37
2.2.6 Power States ............................................................................................................... 38
2.2.7 Address Decoding ....................................................................................................... 38
2.3 INTERRUPT SERIALIZER ........................................................................................................ 38
2.4 PROTECTION ........................................................................................................................... 39
2.4.1 Chassis Intrusion Detection ......................................................................................... 39
2.4.2 Chassis Lock and Unlock ............................................................................................ 39
2.4.3 Access Lock to I/O Ports ............................................................................................. 40
2.4.4 Pin Configuration Lock ................................................................................................ 40
2.4.5 GPIO Pin Function Lock .............................................................................................. 40
5 www.national.com

5 Page





PC87365 arduino
Table of Contents (Continued)
10.3
10.4
10.5
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.7
TOS, THIGH and TLOW Limits, OTS and ALERT Output, IRQ and SMI ...................... 170
ALERT Response Read Sequence ........................................................................... 171
Power-On Reset Default States ................................................................................ 171
Temperature Data Format ......................................................................................... 172
Standby Mode ........................................................................................................... 172
Diode Fault Detection ................................................................................................ 172
TMS REGISTERS ................................................................................................................... 173
10.3.1 TMS Register Map ..................................................................................................... 173
10.3.2 Temperature Event Status Register (TEVSTS) ......................................................... 174
10.3.3 Temperature Event to SMI Register (TEVSMI) ......................................................... 175
10.3.4 Temperature Event to IRQ Register (TEVIRQ) ......................................................... 176
10.3.5 TMS Configuration Register (TMSCFG) .................................................................... 177
10.3.6 TMS Bank Select Register (TMSBS) ......................................................................... 177
10.3.7 Temperature Channel Configuration and Status Register (TCHCFST) .................... 178
10.3.8 Read Channel Temperature Register (RDCHT) ........................................................ 179
10.3.9 Channel Temperature High Limit Register (CHTH) ................................................... 179
10.3.10 Channel Temperature Low Limit Register (CHTL) .................................................... 179
10.3.11 Channel Overtemperature Limit Register (CHOTL) .................................................. 179
TMS REGISTER BITMAP ....................................................................................................... 180
10.4.1 TMS Control and Status Registers .......................................................................... 180
10.4.2 TMS Channel Registers ........................................................................................... 180
USAGE HINTS ........................................................................................................................ 181
10.5.1 Remote Diode Selection ............................................................................................ 181
10.5.2 ADC Noise Filtering ................................................................................................... 181
10.5.3 PC Board Layout ....................................................................................................... 181
10.5.4 Twisted Pair and Shielded Cables ............................................................................. 183
10.5.5 Obtaining the Specified VLM/TMS Accuracy ............................................................. 183
11.0 Legacy Functional Blocks
11.1 KEYBOARD AND MOUSE CONTROLLER (KBC) .................................................................. 184
11.1.1 General Description ................................................................................................... 184
11.1.2 KBC Register Map ..................................................................................................... 184
11.1.3 KBC Bitmap Summary ............................................................................................... 184
11.2 FLOPPY DISK CONTROLLER (FDC) ..................................................................................... 185
11.2.1 General Description ................................................................................................... 185
11.2.2 FDC Register Map ..................................................................................................... 185
11.2.3 FDC Bitmap Summary ............................................................................................... 186
11.3 PARALLEL PORT .................................................................................................................... 187
11.3.1 General Description ................................................................................................... 187
11.3.2 Parallel Port Register Map ......................................................................................... 187
11.3.3 Parallel Port Bitmap Summary .................................................................................. 188
11.4 UART FUNCTIONALITY (SP1 AND SP2) ............................................................................... 190
11.4.1 General Description ................................................................................................... 190
11.4.2 UART Mode Register Bank Overview ....................................................................... 190
11.4.3 SP1 and SP2 Register Maps for UART Functionality ................................................ 191
11 www.national.com

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