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PDF PC33702DWB Data sheet ( Hoja de datos )
| Número de pieza | PC33702DWB | |
| Descripción | 3.0 A Switch-Mode Power Supply with Linear Regulator | |
| Fabricantes | Motorola Inc | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document from Analog Marketing: MC33702/D
Rev 0, 05/2003
Preliminary Information
3.0 A Switch-Mode Power Supply
with Linear Regulator
The 33702 provides the means to efficiently supply the Power QUICC™ I,
II, and other families of Motorola microprocessors and DSPs. The 33702
incorporates a high-performance switching regulator, providing the direct
supply for the microprocessor’s core, and a low dropout (LDO) linear regulator
control circuit providing the microprocessor I/O and bus voltage.
The switching regulator is a high-efficiency synchronous buck regulator with
integrated 50 mΩ N-channel power MOSFETs to provide protection features
and to allow space-efficient, compact design.
The 33702 incorporates many advanced features; e.g., precisely
maintained up/down power sequencing, ensuring the proper operation and
protection of the CPU and power system.
Features
• Operating Voltage: 2.8 V to 6.0 V
• High-Accuracy Output Voltages
• Fast Transient Response
• Switcher Output Current Up to 3.0 A
• Undervoltage Lockout
• Power Sequencing
• Programmable Watchdog Timer
• Voltage Margining via I2C™ Bus
• Overcurrent Protection
• Reset with Programmable Power-ON Delay
• Enable Inputs
I2C is a trademark of Phillips Corporation.
33702
POWER SUPPLY
INTEGRATED CIRCUIT
DWB SUFFIX
CASE 1324-02
32-LEAD SOICW
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC33702DWB/R2 -40 to 85°C
32 SOICW
Op ti on a l
33702 Simplified Application Diagram
22..88VVtoto1 36. 5.0VVIn put
M3C337307023
VVIN22
VVIINN11
VBBDD
VVBBSSTT
SR
RT
LD RV
CS
LDO
ADD R
SDA
SCL
GND
LFB
RES ET
BO OT
EN1
EN2
SW
CLKS YN VVOOUUTT
CLKS EL PG ND
FR E Q
I NV
O the r
Ci r cuits
VLDO =
0.8 t o 5. 0 V
(Adj u sta b l e)
VDDH (I/Os)
MMPPCC88X5xXxX
VBS T
VOUT =
0.8 to 5.0 V
(Adjus table)
PORESET
VDDL (Core)
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2003
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
Supply Voltage
VIN1, VIN2
-0.3 to 7.0
V
Switching Node
SW
-1.0 to 7.0
V
Buck Regulator Bootstrap Input (BOOT - SW)
BOOT
-0.3 to 8.5
V
Boost Regulator Output
VBST
-0.3 to 8.5
V
Boost Regulator Drain
VBD
-0.3 to 9.5
V
RESET Drain Voltage
RESET
-0.3 to 7.0
V
Enable Pins (EN1, EN2)
–
-0.3 to 7.0
V
Logic Pins (SDA, SCL, CLKSYN)
–
-0.3 to 7.0
V
Analog Pins (INV, VOUT, RESET)
–
-0.3 to 7.0
V
Analog Pins (LDRV, LFB, LDO, LCMP, CS)
–
-0.3 to 8.5
V
Analog Pins (CLKSEL, ADDR, RT, FREQ, VDDI)
–
-0.3 to 3.6
V
ESD Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
VESD1
VESD2
±2000
±200
V
Storage Temperature
TSTG
-65 to 150
°C
Power Dissipation (TA = 85°C) (Note 3)
PD
TBD
W
Lead Soldering Temperature (Note 4)
TSOLDER 260 °C
Maximum Junction Temperature
TJMAX
125 °C
Thermal Resistance, Junction to Ambient (Note 5)
RθJA
68 °C/W
Thermal Resistance, Junction to Base (Note 6)
OPERATING CONDITIONS
RθJB
18 °C/W
Supply Voltage (VIN1, VIN2)
VIN1, VIN2
2.8 to 6.0
V
Operational Package Temperature (Ambient Temperature)
TA
-40 to 85
°C
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP=100 pF, RZAP=1500 Ω).
2. ESD2 testing is performed in accordance with the Machine Model (CZAP=200 pF, RZAP=0 Ω).
3. Maximum power dissipation at indicated junction temperature.
4. Lead soldering temperature limit is for 10 seconds maximum duration. Contact Motorola Sales Office for device immersion soldering time/
temperature limits.
5. Thermal resistance measured in accordance with EIA/JESD51-2.
6. Theoretical thermal resistance from the die junction to the exposed pins.
MOTOROLA ANALOG INTEGRATED CIFRCoUrITMDoErVeICEInDfAoTrAmation On This Product,
Go to: www.freescale.com
33702
5
5 Page 
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical
application circuit (see Figure 20) unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
LINEAR REGULATOR (LDO)
LDO Output Current Slew Rate
ISR – TBD – mA/µs
Fault Condition Timeout
tFAULT – 1.0 – ms
Retry Timer Cycle
tRet – 100 – ms
SCA, SCL PIN, I2C BUS (STANDARD)
SCL Clock Frequency
fSCL 0 – 100 kHz
Bus Free Time Between a STOP and a START Condition
tBUF 4.7 –
– µs
Hold Time (Repeated) START Condition (After this period, the first clock pulse
is generated.)
tHD-STA
4.0
–
µs
–
Low Period of the SCL Clock
tLOW 4.7 –
– µs
High Period of the SCL Clock
tHIGH 4.0 –
– µs
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400 pF,
3.0 mA Sink Current
tF
ns
– – 250
Setup Time for a Repeated START Condition
tSU-STA
4.7
–
– µs
Data Hold Time for I2C bus devices (Note 10), (Note 11)
tHD-DAT
0
–
– µs
Data Setup Time
tSU-DAT
250
–
– ns
Setup Time for STOP Condition
tSU-STO
4.0
–
– µs
Capacitive Load for Each Bus Line
CB – – 400 pF
Notes
10. Design Information only. Not production tested.
11. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
Timing Diagram
tHD-STA
tHD-STA
tHD-DAT
tSU-DAT
tSU-STA
Figure 2. Definition of Time on the I2C Bus
MOTOROLA ANALOG INTEGRATED CIFRCoUrITMDoErVeICEInDfAoTrAmation On This Product,
Go to: www.freescale.com
tSU-STO
33702
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PC33702DWB.PDF ] | |
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