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PDF PC16550DV Data sheet ( Hoja de datos )
| Número de pieza | PC16550DV | |
| Descripción | PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1995
PC16550D Universal Asynchronous
Receiver Transmitter with FIFOs
General Description
The PC16550D is an improved version of the original 16450
Universal Asynchronous Receiver Transmitter (UART)
Functionally identical to the 16450 on powerup (CHARAC-
TER mode) the PC16550D can be put into an alternate
mode (FIFO mode) to relieve the CPU of excessive software
overhead
In this mode internal FIFOs are activated allowing 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) to be
stored in both receive and transmit modes All the logic is on
chip to minimize system overhead and maximize system ef-
ficiency Two pin functions have been changed to allow sig-
nalling of DMA transfers
The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM
and parallel-to-serial conversion on data characters re-
ceived from the CPU The CPU can read the complete
status of the UART at any time during the functional opera-
tion Status information reported includes the type and con-
dition of the transfer operations being performed by the
UART as well as any error conditions (parity overrun fram-
ing or break interrupt)
The UART includes a programmable baud rate generator
that is capable of dividing the timing reference clock input
by divisors of 1 to (216b1) and producing a 16 c clock for
driving the internal transmitter logic Provisions are also in-
cluded to use this 16 c clock to drive the receiver logic The
UART has complete MODEM-control capability and a proc-
essor-interrupt system Interrupts can be programmed to
the user’s requirements minimizing the computing required
to handle the communications link
The UART is fabricated using National Semiconductor’s ad-
vanced M2CMOS process
Can also be reset to 16450 Mode under software control
Note This part is patented
Features
Y Capable of running all existing 16450 software
Y Pin for pin compatible with the existing 16450 except
for CSOUT (24) and NC (29) The former CSOUT and
NC pins are TXRDY and RXRDY respectively
Y After reset all registers are identical to the 16450 reg-
ister set
Y In the FIFO mode transmitter and receiver are each
buffered with 16 byte FIFO’s to reduce the number of
interrrupts presented to the CPU
Y Adds or deletes standard asynchronous communication
bits (start stop and parity) to or from the serial data
Y Holding and shift registers in the 16450 Mode eliminate
the need for precise synchronization between the CPU
and serial data
Y Independently controlled transmit receive line status
and data set interrupts
Y Programmable baud generator divides any input clock
by 1 to (216 b 1) and generates the 16 c clock
Y Independent receiver clock input
Y MODEM control functions (CTS RTS DSR DTR RI
and DCD)
Y Fully programmable serial-interface characteristics
5- 6- 7- or 8-bit characters
Even odd or no-parity bit generation and detection
1- 1 - or 2-stop bit generation
Baud generation (DC to 1 5M baud)
Y False start bit detection
Y Complete status reporting capabilities
Y TRI-STATE TTL drive for the data and control buses
Y Line break generation and detection
Y Internal diagnostic capabilities
Loopback controls for communications link
isolation
Break parity overrun framing error simulation
fault
Y Full prioritized interrupt system controls
Basic Configuration
TRI-STATE is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation TL C 8652
TL C 8652 – 1
RRD-B30M75 Printed in U S A
1 page  
3 0 AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions Min Max
Units
Transmitter
tHR Delay from WR WR (WR THR)
to Reset Interrupt
100 pF Load
175 ns
tIR
Delay from RD RD (RD IIR) to Reset
100 pF Load
Interrupt (THRE)
250 ns
tIRS Delay from Initial INTR Reset to Transmit
Start
8
24
BAUDOUT
Cycles
tSI Delay from Initial Write to Interrupt
(Note 1)
16
24
BAUDOUT
Cycles
tSTI Delay from Stop to Interrupt (THRE)
(Note 1)
8
8
BAUDOUT
Cycles
tSXA
Delay from Start to TXRDY active
100 pF Load
8
BAUDOUT
Cycles
tWXI Delay from Write to TXRDY inactive
Modem Control
100 pF Load
195 ns
tMDO
Delay from WR WR (WR MCR) to
Output
100 pF Load
200 ns
tRIM Delay from RD RD to Reset Interrupt 100 pF Load
(RD MSR)
250 ns
tSIM
Delay from MODEM Input to Set Interrupt
100 pF Load
250 ns
Note 1 This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO Interrupt Mode
Operation)
Note 2 These specifications are preliminary
4 0 Timing Waveforms (All timings are referenced to valid 0 and valid 1)
External Clock Input (24 0 MHz Max )
AC Test Points
TL C 8652 – 2
Note 1 The 2 4V and 0 4V levels are the voltages that the inputs are driven to during AC testing
Note 2 The 2 0V and 0 8V levels are the voltages at which the timing tests are made
BAUDOUT Timing
TL C 8652 – 3
TL C 8652 – 4
5
5 Page 
6 0 Pin Descriptions
The following describes the function of all UART pins Some
of these descriptions reference internal circuits
In the following descriptions a low represents a logic 0 (0V
nominal) and a high represents a logic 1 (a2 4V nominal)
A0 A1 A2 Register Select Pins 26–28 Address signals
connected to these 3 inputs select a UART register for the
CPU to read from or write to during data transfer A table of
registers and their addresses is shown below Note that the
state of the Divisor Latch Access Bit (DLAB) which is the
most significant bit of the Line Control Register affects the
selection of certain UART registers The DLAB must be set
high by the system software to access the Baud Generator
Divisor Latches
Register Addresses
DLAB A2 A1 A0
Register
0 0 0 0 Receiver Buffer (read)
Transmitter Holding
Register (write)
0 0 0 1 Interrupt Enable
X 0 1 0 Interrupt Identification (read)
X 0 1 0 FIFO Control (write)
X 0 1 1 Line Control
X 1 0 0 MODEM Control
X 1 0 1 Line Status
X 1 1 0 MODEM Status
X 1 1 1 Scratch
1 0 0 0 Divisor Latch
(least significant byte)
1 0 0 1 Divisor Latch
(most significant byte)
ADS Address Strobe Pin 25 The positive edge of an active
Address Strobe (ADS) signal latches the Register Select
(A0 A1 A2) and Chip Select (CS0 CS1 CS2) signals
Note An active ADS input is required when the Register Select (A0 A1 A2)
and Chip Select (CS0 CS1 CS2) signals are not stable for the dura-
tion of a read or write operation If not required tie the ADS input
permanently low
BAUDOUT Baud Out Pin 15 This is the 16 c clock signal
from the transmitter section of the UART The clock rate is
equal to the main reference oscillator frequency divided by
the specified divisor in the Baud Generator Divisor Latches
The BAUDOUT may also be used for the receiver section by
tying this output to the RCLK input of the chip
CS0 CS1 CS2 Chip Select Pins 12–14 When CS0 and
CS1 are high and CS2 is low the chip is selected This
enables communication between the UART and the CPU
The positive edge of an active Address Strobe signal latch-
es the decoded chip select signals completing chip selec-
tion If ADS is always low valid chip selects should stabilize
according to the tCSW parameter
CTS Clear to Send Pin 36 When low this indicates that
the MODEM or data set is ready to exchange data The CTS
signal is a MODEM status input whose conditions can be
tested by the CPU reading bit 4 (CTS) of the MODEM Status
Register Bit 4 is the complement of the CTS signal Bit 0
(DCTS) of the MODEM Status Register indicates whether
the CTS input has changed state since the previous reading
of the MODEM Status Register CTS has no effect on the
Transmitter
Note Whenever the CTS bit of the MODEM Status Register changes state
an interrupt is generated if the MODEM Status Interrupt is enabled
D7 – D0 Data Bus Pins 1 – 8 This bus comprises eight TRI-
STATE input output lines The bus provides bidirectional
communications between the UART and the CPU Data
control words and status information are transferred via the
D7 – D0 Data Bus
DCD Data Carrier Detect Pin 38 When low indicates that
the data carrier has been detected by the MODEM or data
set The DCD signal is a MODEM status input whose condi-
tion can be tested by the CPU reading bit 7 (DCD) of the
MODEM Status Register Bit 7 is the complement of the
DCD signal Bit 3 (DDCD) of the MODEM Status Register
indicates whether the DCD input has changed state since
the previous reading of the MODEM Status Register DCD
has no effect on the receiver
Note Whenever the DCD bit of the MODEM Status Register changes state
an interrupt is generated if the MODEM Status Interrupt is enabled
DDIS Driver Disable Pin 23 This goes low whenever the
CPU is reading data from the UART It can disable or control
the direction of a data bus transceiver between the CPU
and the UART
DSR Data Set Ready Pin 37 When low this indicates that
the MODEM or data set is ready to establish the communi-
cations link with the UART The DSR signal is a MODEM
status input whose condition can be tested by the CPU
reading bit 5 (DSR) of the MODEM Status Register Bit 5 is
the complement of the DSR signal Bit 1 (DDSR) of the
MODEM Status Register indicates whether the DSR input
has changed state since the previous reading of the MO-
DEM Status Register
Note Whenever the DDSR bit of the MODEM Status Register changes
state an interrupt is generated if the MODEM Status Interrupt is en-
abled
DTR Data Terminal Ready Pin 33 When low this informs
the MODEM or data set that the UART is ready to establish
a communications link The DTR output signal can be set to
an active low by programming bit 0 (DTR) of the MODEM
Control Register to a high level A Master Reset operation
sets this signal to its inactive (high) state Loop mode opera-
tion holds this signal in its inactive state
INTR Interrupt Pin 30 This pin goes high whenever any
one of the following interrupt types has an active high condi-
tion and is enabled via the IER Receiver Error Flag Re-
ceived Data Available timeout (FIFO Mode only) Transmit-
ter Holding Register Empty and MODEM Status The INTR
signal is reset low upon the appropriate interrupt service or
a Master Reset operation
MR Master Reset Pin 35 When this input is high it clears
all the registers (except the Receiver Buffer Transmitter
Holding and Divisor Latches) and the control logic of the
UART The states of various output signals (SOUT INTR
OUT 1 OUT 2 RTS DTR) are affected by an active MR
input (Refer to Table I ) This input is buffered with a TTL-
compatible Schmitt Trigger with 0 5V typical hysteresis
OUT 1 Output 1 Pin 34 This user-designated output can
be set to an active low by programming bit 2 (OUT 1) of the
MODEM Control Register to a high level A Master Reset
operation sets this signal to its inactive (high) state Loop
mode operation holds this signal in its inactive state In the
XMOS parts this will achieve TTL levels
11
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| PDF Descargar | [ Datasheet PC16550DV.PDF ] | |
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