QS5LV91970J Datasheet PDF - Integrated Device Technology
| Part Number | QS5LV91970J | |
| Description | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER | |
| Manufacturers | Integrated Device Technology | |
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QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
INDUSTRIALTEMPERATURERANGE
QS5LV919
FEATURES:
• 3.3V operation
• JEDEC compatible LVTTL level outputs
• Clock inputs are 5V tolerant
• < 300ps output skew, Q0–Q4
• 2xQ output, Q outputs, Q output, Q/2 output
• Outputs 3-state and reset while OE/RST low
• PLL disable feature for low frequency testing
• Internal loop filter RC network
• Functional equivalent to MC88LV915, IDT74FCT388915
• Positive or negative edge synchronization (PE)
• Balanced drive outputs ±24mA
• 160MHz maximum frequency (2xQ output)
• Available in QSOP and PLCC packages
DESCRIPTION:
The QS5LV919 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to one of two reference clock inputs.
Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and
design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs.
The QS5LV919 includes an internal RC filter which provides excellent
jitter characteristics and eliminates the need for external components.
Various combinations of feedback and a divide-by-2 in the VCO path
allow applications to be customized for linear VCO operation over a
wide range of input SYNC frequencies. The PLL can also be disabled
by the PLL_EN signal to allow low frequency or DC testing. The LOCK
output asserts to indicate when phase lock has been achieved. The
QS5LV919 is designed for use in high-performance workstations, multi-
board computers, networking hardware, and mainframe systems. Sev-
eral can be used in parallel or scattered throughout a system for guar-
anteed low skew, system-wide clock distribution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
O E /R S T
SYNC0
SYNC1
REF_SEL
0
LOCK PE
FEEDBACK
1
PHASE
LOOP
DETECTOR
FILTER
VCO
PLL_EN
FREQ_SEL
01
1 /2 0
RDR DR DRDR DR DRD
Q Q Q Q Q Q QQ
Q /2 Q5 Q4 Q3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2001 Integrated Device Technology, Inc.
1
Q2
Q1 Q0
2xQ
JULY 2001
DSC-5820/3
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QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIALTEMPERATURERANGE
INPUT TIMING REQUIREMENTS
Symbol
Description(1)
Min. Max.
Unit
tR, tF Maximum input rise and fall times, 0.8V to 2V
—3
ns
FI Input Clock Frequency, SYNC0, SYNC1(1)
2.5 100 MHz
tPWC Input clock pulse, HIGH or LOW(2)
2—
ns
DH Input duty cycle, SYNC0, SYNC1(2)
25 75
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and
FREQ_SEL combinations.
2. Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter(1)
Min.
tSKR
tSKF
tSKALL
tPW
tPW
tJ
tPD
tLOCK
tPZH
tPZL
tPHZ
tPLZ
tR, tF
Output Skew Between Rising Edges, Q0-Q4 (and Q/2 if PE = LOW)(2)
Output Skew Between Falling Edges, Q0-Q4 (and Q/2 if PE = HIGH)(2)
Output Skew, All Outputs(2, 5)
Pulse Width, 2xQ output, >40MHz
Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter(4)
SYNC Input to Feedback Delay(6)
SYNC to Phase Lock
Output Enable Time, OE/RST LOW to HIGH(3)
Output Disable Time, OE/RST HIGH to LOW(3)
Output Rise/Fall Times, 0.8V ∼ 2V
—
—
—
TCY/2 − 0.4
TCY/2 − 0.4
− 0.15
− 500
—
0
0
0.3
Max.
300
300
500
TCY/2 + 0.4
TCY/2 + 0.4
0.15
0
10
14
14
2
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. Skew measured at selected synchronization edge.
6. tPD measured at device inputs at 0.5VDD, Q output at 80MHz.
Unit
ps
ps
ps
ns
ns
ns
ps
ms
ns
ns
ns
5
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Featured Datasheets
| Part Number | Description | MFRS |
| QS5LV91970J | The function is 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER. Integrated Device Technology | |
| QS5LV91970Q | The function is 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER. Integrated Device Technology | |
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