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QL8025 fiches techniques PDF

ETC - LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM

Numéro de référence QL8025
Description LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
Fabricant ETC 
Logo ETC 





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QL8025 fiche technique
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‡ 0.18 µ, six layer metal CMOS process
‡ 1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O
‡ Up to 4,008 dedicated flip-flops
‡ Up to 55.3 K embedded RAM Bits
‡ Up to 313 I/O
‡ Up to 370 K system gates
‡ IEEE 1149.1 Boundary Scan Testing
Compliant
‡ Low Power Capability
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‡ Up to twenty-four 2,304 bit Dual Port High
Performance SRAM Blocks
‡ Up to 55,296 embedded RAM bits
‡ RAM/ROM/FIFO Wizard for automatic
configuration
‡ Configurable and cascadable
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‡ High performance I/O cell with Tco< 3 ns
‡ Programmable Slew Rate Control
‡ Programmable I/O Standards:
‡ LVTTL, LVCMOS, LVCMOS18, PCI,
GTL+, SSTL2, and SSTL3
‡ Independent I/O Banks capable of
supporting multiple standards in one device
‡ I/O Register Configurations: Input,
Output, Output Enable (OE)
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‡ Multiple dedicated Low Skew Clock
Networks
‡ High drive input-only networks
‡ Quadrant-based segmentable clock networks
‡ User Programmable Phase Locked Loops
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Hardwired DSP building blocks with integrated
Multiply, Add, and Accumulate Functions.
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The QuickLogic products come with secure
ViaLinktechnology that protects intellectual
property from design theft and reverse
engineering. No external configuration memory
needed; Instant-on at Power-up.
PLL Embedded RAM Blocks
Embeded Computational Units
PLL
Fabric
PLL Embedded RAM Blocks
PLL
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