PBM3960 Datasheet PDF - Ericsson
| Part Number | PBM3960 | |
| Description | Microstepping Controller/Dual Digital-to-Analog Converter | |
| Manufacturers | Ericsson | |
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February 1999
PBM 3960/1
Microstepping Controller/
Dual Digital-to-Analog Converter
Description
PBM 3960/1 is a dual 7-bit+sign, Digital-to-Analog Converter (DAC) especially
developed to be used together with the PBL 3771/1, Precision Stepper Motor driver
in micro-stepping applications. The circuit has a set of input registers connected to an
8-bit data port for easy interfacing directly to a microprocessor. Two registers are
used to store the data for each seven-bit DAC, the eighth bit being a sign bit (sign/
magnitude coding). A second set of registers are used for automatic fast/slow current
decay control in conjunction with the PBL 3771/1, a feature that greatly improves
high-speed micro-stepping performance. The PBM 3960/1 is fabricated in a high-
speed CMOS process.
Key Features
• Analog control voltages from 3 V
down to 0.0 V.
• High-speed microprocessor interface.
• Automatic fast/slow current decay
control.
• Full-scale error ±1 LSB.
• Interfaces directly with TTL levels and
CMOS devices.
• Fast conversion speed, 3 µs.
• Matches PBL 3771.
WR
CS
A0
A1
D7 - D0
RESET
VDD
VRef
POR
DA- Data 1
E
C
D
E1 R
Level 1
E
E2
C
D
R
Level 2
E3 E
C
D
E4 R
DA- Data 2
E
C
D
R
R
Digit
Comp
E1 E
C
D
R
Digit
Comp
E4
C
E
D
R
Vss
PBM 3960/1
Sign 1
D/A
CD1
DA 1
D/A
DA 2
CD2
Sign 2
Figure 1. Block Diagram.
22-pin plastic DIP
28-pin plastic PLCC
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PBM 3960/1
Definition of Terms
Resolution
Resolution is defined as the reciprocal of
the number of discrete steps in the DAC
output. It is directly related to the
number of switches or bits within the
DAC. For example, PBM 3960/1 has 27,
or 128, output levels and therefor has 7
bits resolution. Remember that this is
not equal to the number of microsteps
available.
Linearity Error
Linearity error is the maximum deviation
from a straight line passing through the
end points of the DAC transfer
characteristic. It is measured after
adjusting for zero and full scale.
Linearity error is a parameter intrinsic to
the device and cannot be externally
adjusted.
Power Supply Sensitivity
Power supply sensitivity is a measure of
the effect of power supply changes on
the DAC full-scale output.
Settling Time
Full-scale current settling time requires
zero-to-full-scale or full-scale-to-zero
output change. Settling time is the time
required from a code transition until the
DAC output reaches within ±1/2LSB of
the final output value.
Full-scale Error
Full-scale error is a measure of the
output error between an ideal DAC and
the actual device output.
Differential Non-linearity
The difference between any two
consecutive codes in the transfer curve
from the theoretical 1LSB, is differential
non-linearity
Monotonic
If the output of a DAC increases for
increasing digital input code, then the
DAC is monotonic. A 7-bit DAC which is
monotonic to 7 bits simply means that
increasing digital input codes will
produce an increasing analog output.
PBM 3960/1 is monotonic to 7 bits.
Functional Description
Each DAC channel contains two
registers, a digital comparator, a flip flop,
and a D/A converter. A block diagram is
shown on the first page. One of the
registers stores the current level, below
which, fast current decay is initiated.
The status of the CD outputs determines
a fast or slow current decay to be used
in the driver.
The digital comparator compares
each new value with the previous one
and the value for the preset level for fast
current decay. If the new value is strictly
lower than both of the others, a fast
current decay condition exists. The flip
flop sets the CD output. The CD output
is updated each time a new value is
loaded into the D/A register. The fast
current decay signals are used by the
driver circuit, PBL 3771/1, to change the
current control scheme of the output
stages. This is to avoid motor current
dragging which occurs at high stepping
rates and during the negative current
slopes, as illustrated in figure 9. Eight
different levels for initiation of fast
current decay can be selected.
The sign outputs generate the phase
shifts, i.e., they reverse the current
direction in the phase windings.
Data Bus Interface
PBM 3960/1 is designed to be compat-
ible with 8-bit microprocessors such as
the 6800, 6801, 6803, 6808, 6809, 8051,
8085, Z80 and other popular types and
their 16/32 bit counter parts in 8 bit data
mode. The data bus interface consists of
8 data bits, write signal, chip select, and
two address pins. All inputs are TTL-
compatible (except reset). The two
address pins control data transfer to the
four internal D-type registers. Data is
transferred according to figure 10 and on
the positive edge of the write signal.
Current
Direction,
Sign1
&
Sign
2
These bits are transferred from D7 when
writing in the respective DA register. A0
and A1 must be set according to the data
transfer table in figure 10.
Current Decay, CD1 & CD2
CD1 and CD2 are two active low signals
(LOW = fast current decay). CD is
1
active if the previous value of DA-Data1
is strictly larger than the new value of
DA-Data1 and the value of the level
register LEVEL1 (L61 … L41) is strictly
larger than the new value of DA-Data1.
CD1 is updated every time a new value
is loaded into DA-Data1. The logic
definition of CD1 is:
CD1 = NOT{[(D6 … D0) < (Q61 … Q01)]
AND[(D6 …D4) < (L61 … L41)]}
Output
More
than 2
bits
Negative
difference
Input
Figure 5. Errors in D/A conversion.
Differential non-linearity of more than 1
bit, output is non-monotonic.
Output
Less
than 2
bits
Output
Actual
Gain
error
Correct
Endpoint
non-linearity
Positive
difference
Input
Offset error
Full scale Input
Figure 6. Errors in D/A conversion.
Differential non-linearity of less than 1 bit,
output is monotonic.
Figure 7. Errors in D/A conversion. Non-
linearity, gain and offset errors.
5
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| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ PBM3960.PDF Datasheet ] | |
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