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PDF RC5051 Data sheet ( Hoja de datos )
| Número de pieza | RC5051 | |
| Descripción | Programmable Synchronous DC-DC Controller for Low Voltage Microprocessors | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.fairchildsemi.com
RC5051
Programmable Synchronous DC-DC Controller for
Low Voltage Microprocessors
Features
• Programmable output from 1.3V to 3.5V using an
integrated 5-bit DAC
• 85% efficiency typical
• Adjustable operation from 80KHz to 1MHz
• Integrated Power Good and Enable functions
• Overvoltage protection
• Overcurrent protection
• Drives N-channel MOSFETs
• 20 pin SOIC package
• Meets Intel Pentium II specifications using minimum
number of external components
Applications
• Power supply for Pentium® II
• VRM for Pentium II processor
• Programmable step-down power supply
Description
The RC5051 is a synchronous mode DC-DC controller IC
which provides an accurate, programmable output voltage
for all Pentium II CPU applications. The RC5051 uses a
5-bit D/A converter to program the output voltage from 1.3V
to 3.5V. The RC5051 uses a high level of integration to
deliver load currents in excess of 19A from a 5V source with
minimal external circuitry. Synchronous-mode operation
offers optimum efficiency over the entire specified output
voltage range, and the internal oscillator can be programmed
from 80KHz to 1MHz for additional flexibility in choosing
external components. An on-board precision low TC refer-
ence achieves tight tolerance voltage regulation without
expensive external components. The RC5051 also offers
integrated functions including Power Good, Output Enable,
over-voltage protection and current limiting.
Block Diagram
1
OSC
+12V
RC5051
5
–
4
+
+5V
– 13
+ 12
– DIGITAL
– + CONTROL
+
+5V
7
9
VO
VREF 16
5-BIT
DAC
1.24V
REFERENCE
20 19 18 17 8
VID0 VID2 VID4
VID1 VID3
2
ENABLE
POWER
GOOD
3
PWRGD
65-5051-01
Pentium is a registered trademark of Intel Corporation.
REV. 1.0.4 4/2/01
1 page  
PRODUCT SPECIFICATION
RC5051
Typical Operating Characteristics
(VCCA, VCCD = 5V, fOSC = 280 KHz, and TA = +25°C using circuit in Figure 1, unless otherwise noted)
88.0
86.0
84.0
82.0
80.0
78.0
76.0
74.0
72.0
70.0
1
Efficiency vs. Output Current
VOUT = 2.0V
VOUT = 2.8V
3 5 7 9 11 13 14.5
Output Current (A)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
Output Voltage vs. Output Current,
RSENSE = 6mΩ
5 10 15 20
Output Current (A)
25
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
2.73
1
Load Regulation, VOUT = 2.8 V
3 5 7 9 11 13 14.5
Output Current (A)
1250
1050
850
650
450
250
50
18
Oscillator Frequency vs. CEXT
39 75 150 300 560
CEXT (pf)
Output Programming, VID4 = 0
3.5
3.0
2.5
2.0
1.5
1.0
1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00
DAC Set Point
Output Programming, VID4 = 1
3.5
3.0
2.5
2.0
1.5
1.0
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
DAC Set Point
65-5050-03
REV. 1.0.4 4/2/01
5
5 Page 
PRODUCT SPECIFICATION
RC5051
developed across the sense resistor exceeds the 120mV com-
parator threshold voltage, the RC5051 reduces the output
duty cycle to help protect the power devices. The DC-DC
converter returns to normal operation after the fault has been
removed.
Oscillator
The RC5051 oscillator section uses a fixed current capacitor
charging configuration. An external capacitor (CEXT) is
used to set the oscillator frequency between 80KHz and
1MHz. This scheme allows maximum flexibility in choosing
external components.
In general, a higher operating frequency decreases the peak
ripple current flowing in the output inductor, thus allowing
the use of a smaller inductor value. In addition, operation at
higher frequencies decreases the amount of energy storage
that must be provided by the bulk output capacitors during
load transients due to faster loop response of the controller.
Unfortunately, the efficiency losses due to switching of the
MOSFETs increase as the operating frequency is increased.
Thus, efficiency is optimized at lower frequencies. An oper-
ating frequency of 300KHz is a typical choice which opti-
mizes efficiency and minimizes component size while
maintaining excellent regulation and transient performance
under all operating conditions.
Design Considerations and Component
Selection
Additional information on design and component selection
may be found in Fairchild Semiconductor’s Application
Note 53.
MOSFET Selection
This application requires N-channel Logic Level Enhance-
ment Mode Field Effect Transistors. Desired characteristics
are as follows:
• Low Static Drain-Source On-Resistance,
RDS,ON < 20mΩ (lower is better)
• Low gate drive voltage, VGS = 4.5V rated
• Power package with low Thermal Resistance
• Drain-Source voltage rating > 15V.
The on-resistance (RDS,ON) is the primary parameter for
MOSFET selection. The on-resistance determines the power
dissipation within the MOSFET and therefore significantly
affects the efficiency of the DC-DC Converter. For details
and a spreadsheet on MOSFET selection, refer to Applica-
tions Bulletin AB-8
MOSFET Gate Bias
The high side MOSFET gate driver can be biased by one of
two methods–Charge Pump or 12V Gate Bias. The charge
pump method has the advantage of requiring only +5V as an
input voltage to the converter, but the 12V method will real-
ize increased efficiency by providing an increased VGS to the
high side MOSFETs.
Method 1. Charge Pump (Bootstrap)
Figure 3 shows the use of a charge pump to provide gate bias
to the high side MOSFET when +12V is unavailable. Capac-
itor CP is the charge pump used to boost the voltage of the
RC5051 output driver. When the MOSFET Q1 switches off,
the source of the MOSFET is at approximately 0V because
of the MOSFET Q2. (The Schottky D2 conducts for only a
very short time, and is not relevent to this discussion.) CP is
charged through the Schottky diode D1 to approximately
4.5V. When the MOSFET Q1 turns on, the voltage at the
source of the MOSFET is equal to 5V. The capacitor voltage
follows, and hence provides a voltage at VCCQP equal to
almost 10V. The Schottky diode D1 is required to provide
the charge path when the MOSFET is off, and reverses
biases when VCCQP goes to 10V. The charge pump capaci-
tor (CP) needs to be a high Q, high frequency capacitor. A
1µF ceramic capacitor is recommended here.
+5V
PWM/PFM
Control
VCCQP
D1
HIDRV
CP
LODRV
GNDP
Q1
L2 RS
VO
COUT
Q2
D2
65-5051-06
Figure 3. Charge Pump Configuration
Method 2. 12V Gate Bias
Figure 4 illustrates how a 12V source can be used to bias
VCCQP. A 47Ω resistor is used to limit the transient current
into the VCCQP pin and a 1µF capacitor is used to filter the
VCCQP supply. This method provides a higher gate bias
voltage (VGS) to the high side MOSFET than the charge
pump method, and therefore reduces the RDS,ON and the
resulting power loss within the MOSFET. In designs where
efficiency is a primary concern, the 12V gate bias method is
recommended. A 6.2V Zener diode, D1, is used to clamp the
voltage at VCCQP to a maximum of 12V and ensure that the
absolute maximum voltage of the IC will not be exceeded.
REV. 1.0.4 4/2/01
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet RC5051.PDF ] | |
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