RF1S42N03LSM Datasheet PDF - Intersil Corporation
| Part Number | RF1S42N03LSM | |
| Description | 42A/ 30V/ 0.025 Ohm/ Logic Level/ N-Channel Power MOSFET | |
| Manufacturers | Intersil Corporation | |
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Data Sheet
RFP42N03L, RF1S42N03LSM
July 1999 File Number 4302.2
42A, 30V, 0.025 Ohm, Logic Level,
N-Channel Power MOSFET
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49030.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFP42N03L
TO-220AB
FP42N03L
RF1S42N03LSM TO-263AB
F42N03L
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, e.g., RF1S42N03LSM9A.
Packaging
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
Features
• 42A, 30V
• rDS(ON) = 0.025Ω
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, and TTL
Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
6-267
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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RFP42N03L, RF1S42N03LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
VGS = VDS, ID = 250µA
1.5
2.0 ID = 250µA
1.5
1.0 1.0
0.5 0.5
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2500
2000
1500
CISS
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
1000
500
00
COSS
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-271
0
-80 -40
0
40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
30
VDD = BVDSS
24
VDD = BVDSS
5
4
18
0.75 BVDSS
0.50 BVDSS
12 0.25 BVDSS
3
2
6
RL = 0.714Ω
IG(REF) = 0.6mA
1
VGS = 5V
00
20 I-I-GG-----((--AR----CE----FT----))
t, TIME (µs)
80 I-I-GG-----((--AR----CE----FT----))
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
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| Information | Total 8 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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