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PDF RF1S40N10LESM Data sheet ( Hoja de datos )
| Número de pieza | RF1S40N10LESM | |
| Descripción | 40A/ 100V/ 0.040 Ohm/ Logic Level N-Channel Power MOSFETs | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Data Sheet
October 1999 File Number 4061.5
40A, 100V, 0.040 Ohm, Logic Level
N-Channel Power MOSFETs
These N-Channel enhancement mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49163.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFG40N10LE
TO-247
FG40N10L
RFP40N10LE
TO-220AB
FP40N10L
RF1S40N10LESM TO-263AB
F40N10LE
NOTE: When ordering, use the entire part number. Add the suffix, 9A, to
obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A.
Packaging
DRAIN
(FLANGE)
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
Features
• 40A, 100V
• rDS(ON) = 0.040Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RFG40N10LE, RFP40N10LE, RF1S40N10LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
1.50
VGS = VDS, ID = 250µA
1.25
1.50
ID = 250µA
1.25
1.00
1.00
0.75
0.75
0.50
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
3500
2800
2100
1400
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
CISS
700
0
0
COSS
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
5
0.50
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
100 5.00
VDD = BVDSS
75
VDD = BVDSS
3.75
RL = 2.5Ω
IG(REF) = 1.7mA
50 VGS = 5V
2.50
PLATEAU VOLTAGES IN
DESCENDING ORDER:
25
VDD = BVDSS
VDD = 0.75 BVDSS
1.25
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
00
20 I-I-GG-----((--AR----CE----FT----)) t, TIME (µs)
80 I-I-GG-----((--AR----CE----FT----))
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. SWITCHING WAVEFORMS FOR CONSTANT GATE
CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet RF1S40N10LESM.PDF ] | |
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