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PDF RF1K49154 Data sheet ( Hoja de datos )

Número de pieza RF1K49154
Descripción 2A/ 60V/ 0.130 Ohm/ Dual N-Channel/ LittleFET Power MOSFET
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
RF1K49154
October 1999 File Number 4143.3
2A, 60V, 0.130 Ohm, Dual N-Channel,
LittleFET™ Power MOSFET
This Dual N-Channel power MOSFET is manufactured using
the latest manufacturing process technology. This process,
which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It is designed for use
in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. These devices can be operated directly from
integrated circuits.
Formerly developmental type TA49154.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RF1K49154
MS-012AA
RF1K49154
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e., RF1K4915496.
Features
• 2A, 60V
• rDS(ON) = 0.130
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D1(8)
D1(7)
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999.

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RF1K49154 pdf
RF1K49154
Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued)
1.5
ID = 250µA
500
400
1.25
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
300
1
COSS
200
0.75
100 CRSS
0.5
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
0
0 5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
60 10
45
VDD = BVDSS
RL = 30
30
IG(REF) = 0.26mA
VGS = 10V
PLATEAU VOLTAGES IN
DESCENDING ORDER:
15 VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
0
20 I-I-GG-----((--AR----CE----FT----)) t, TIME (µs)
80 I-I-GG-----((--AR----CE----FT----))
7.5
5
2.5
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01
0
tP
IAS
BVDSS
tAV
VDS
VDD
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
5

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