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PDF RFD20N03SM Data sheet ( Hoja de datos )
| Número de pieza | RFD20N03SM | |
| Descripción | 20A/ 30V/ 0.025 Ohm/ N-Channel Power MOSFETs | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
RFD20N03, RFD20N03SM
July 1999 File Number 4350.1
20A, 30V, 0.025 Ohm, N-Channel Power
MOSFETs
The RFD20N03 and RFD20N03SM N-Channel power
MOSFETs are manufactured using the MegaFET process.
This process which uses feature sizes approaching those of
LSI integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use in applications such as switching regulators,
switching converters, motor drivers, and relay drivers. These
transistors can be operated directly from integrated circuits.
Formerly developmental type TA49235.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD20N03
TO-251AA
F20N03
RFD20N03SM
TO-252AA
F20N03
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in tape and reel, e.g., RFD20N03SM9A.
Packaging
JEDEC TO-251AA
Features
• 20A, 30V
• rDS(ON) = 0.025Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
4-427
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RFD20N03, RFD20N03SM
Typical Performance Curves (Continued)
1800
1500
1200
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
900
600
CRSS
300
COSS
0
0 10 20 30
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
VDD = 15V
8
6
4 WAVEFORMS IN
DESCENDING ORDER:
2
ID = 20A
ID = 15A
ID = 10A
ID = 5A
0
0 6 12 18 24 30
Qg, GATE CHARGE (nC)
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
0
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VGS
Ig(REF)
VDS
RL
DUT
+
VDD
-
FIGURE 16. GATE CHARGE TEST CIRCUIT
4-431
VDD
VDS
Qg(TOT)
VGS
VGS = 2V
0
Qg(10)
Qg(TH)
VGS = 10V
VGS = 20V
Ig(REF)
0
FIGURE 17. GATE CHARGE WAVEFORM
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet RFD20N03SM.PDF ] | |
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