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PDF RFD10P03L Data sheet ( Hoja de datos )
| Número de pieza | RFD10P03L | |
| Descripción | 10A/ 30V/ 0.200 Ohm/ Logic Level/ P-Channel Power MOSFET | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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RFD10P03L, RFD10P03LSM, RFP10P03L
Data Sheet
July 1999 File Number 3515.2
10A, 30V, 0.200 Ohm, Logic Level,
P-Channel Power MOSFET
These products are P-Channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
Formerly developmental type TA49205.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD10P03L
TO-251AA
10P03L
RFD10P03LSM
TO-252AA
10P03L
RFP10P03L
TO-220AB
F10P03L
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-252AA variant in tape and reel, i.e. RFD10P03LSM9A..
Packaging
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
Features
• 10A, 30V
• rDS(ON) = 0.200Ω
• Temperature Compensating PSPICE® Model
• PSPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
Symbol
D
G
S
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
7-3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RFD10P03L, RFD10P03LSM, RFP10P03L
Typical Performance Curves Unless Otherwise Specified (Continued)
1.2
VGS = VDS, ID = -250µA
1.0
0.8
0.6
0.4
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
-30
-22.5
VDD =BVDSS
VDD = BVDSS
-5.00
-3.75
RL = 3.0Ω
-15 IG(REF) = -0.25mA -2.50
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
-7.5
0.25 BVDSS 0.25 BVDSS
-1.25
VGS = -5V
0
IG(REF)
20
IG(ACT)
t, TIME ( µs)
IG(REF)
80
IG(ACT)
0.00
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
150
VDD = -15V, ID = -10A, RL= 1.50Ω
125
100
75
50
25
tr
td(OFF)
tf
td(ON)
0
0 10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
1200
1000
800
600
400
200
0
0
CISS
COSS
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
CRSS
-5 -10 -15 -20
VDS, DRAIN TO SOURCE VOLTAGE (V)
-25
FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
tP
RG
VDS
L
DUT
-
VDD
+
IAS
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
tAV
0
VDD
IAS
tP
BVDSS
VDS
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
7-7
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet RFD10P03L.PDF ] | |
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