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PDF RF2469 Data sheet ( Hoja de datos )

Número de pieza RF2469
Descripción W-CDMA AND PCS LOW NOISE AMPLIFIER/MIXER DOWNCONVERTER
Fabricantes RF Micro Devices 
Logotipo RF Micro Devices Logotipo



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Preliminary
8
Typical Applications
• W-CDMA Handsets
• PCS Handsets
• General Purpose Downconverter
RF2469
W-CDMA AND PCS LOW NOISE
AMPLIFIER/MIXER DOWNCONVERTER
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
Product Description
The RF2469 is a receiver front-end designed for the
receive section of W-CDMA and PCS applications. It is
designed to amplify and downconvert RF signals while
providing 23dB of stepped gain control range and fea-
tures digital control of the LNA gain and mixer gain. A fur-
ther feature of the chip is adjustable IIP3 of the LNA and
mixer using an off-chip current setting resistor. Noise Fig-
ure, IP3, and other specs are designed to be compatible
with W-CDMA and PCS communications. The IC is man-
ufactured on an advanced Gallium Arsenide Heterojunc-
tion Bipolar Transistor (GaAs HBT) process and
packaged in a 20-pin, leadless chip carrier with an
exposed die flag.
1.00
0.90
0.60
0.24 typ
3 0.20
4.00
sq.
0.65
0.30
4 PLCS
2.10
sq.
12°
MAX
0.75
0.50
0.05
0.50
Dimensions in mm.
NOTES:
1 Shaded lead is Pin 1.
Note orientation of package.
2 Pin 1 identifier must exist on top surface of package by identification
mark or feature on the package body. Exact shape and size is optional.
3 Dimension applies to plated terminal: to be measured between 0.02 mm
and 0.25 mm from terminal end.
4 Package Warpage: 0.05 mm max.
5 Die Thickness Allowable: 0.305 mm max.
0.23
0.13
4 PLCS
Optimum Technology Matching® Applied
Si BJT
üGaAs HBT
GaAs MESFET
Si Bi-CMOS
SiGe HBT
Si CMOS
20 19 18 17 16
LNA1 OUT 1
15 LNA1 BYP
GND 2
VCC1 3
Logic
Control
14
LNA2
BYP
13 GND
VCC1 4
12 VCC1
LNA2 IN 5
11 LO IN
6 7 8 9 10
Functional Block Diagram
Package Style: LCC, 20-Pin, 4x4
Features
• Complete Receiver Front-End
• Stepped LNA/Mixer Gain Control
• Adjustable LNA/Mixer Bias Current
• 23dB Maximum Cascade Gain
• 2.5dB Noise Figure at Maximum
Cascade Gain
Ordering Information
RF2469
RF2469 PCBA
W-CDMA and PCS Low Noise Amplifier/Mixer Down-
converter
Fully Assembled Evaluation Board
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
8
Rev A5 010717
8-33

1 page




RF2469 pdf
Preliminary
RF2469
Pin Function Description
Interface Schematic
15 LNA1 BYP Logic control for LNA1 gain. A logic high (>2.4V) places LNA1 in the
high gain mode. A logic low (<0.3V) place LNA1 in the bypass mode.
LNA1 BYP
32 k
16 ENABLE A logic control for mixer and LO buffer. A logic high (>2.4V) turn the
mixer and LO buffer on. A logic low (<0.3V) disable the mixer and LO
buffer.
ENABLE
32 k
17
VCC1
Supply voltage for the mixer. An external resistor is place in series with
this pin to adjust the mixer current. A nominal value of 1000set the
mixer current to ~10mA. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Con-
nect ground sides of caps directly to ground.
18
VCC1
Supply voltage for IC. External RF bypassing is required. The trace
length between the bypass caps and the pin should be minimized. Con-
nect ground sides of caps directly to ground.
19 LNA1 IN RF input to LNA1. This pin is internally DC-biased and, if it is con-
nected to a device with DC present, should be DC-blocked with a
capacitor suitable for the frequency of operation.
LNA1 IN
20
Pkg
Base
GND
GND
Ground connection. For best performance, keep traces physically short
and connect directly to ground plane.
Ground connection. The backside of the package should be soldered to
a top side ground pad which is connected to the ground plane with mul-
tiple vias.
8
Rev A5 010717
8-37

5 Page





RF2469 arduino
Preliminary
RF2469
Evaluation Board Layout
Board Size 2.0” x 2.0”
Board Thickness 0.031”, Board Material FR-4, Multi-Layer
Assembly
Top
Power Plane
8
Back
Rev A5 010717
8-43

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