RLD03N06CLESM Datasheet PDF - Fairchild Semiconductor
| Part Number | RLD03N06CLESM | |
| Description | 0.3A/ 60V/ ESD Rated/ Current Limited/ Voltage Clamped Logic Level N-Channel Enhancement-Mode Power MOSFETs | |
| Manufacturers | Fairchild Semiconductor | |
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RLD03N06CLE,
S E M I C O N D U C T O R RLD03N06CLESM, RLP03N06CLE
July 1996
0.3A, 60V, ESD Rated, Current Limited, Voltage Clamped
Logic Level N-Channel Enhancement-Mode Power MOSFETs
Features
• 0.30A, 60V
• rDS(ON) = 6.0Ω
• Built in Current Limit ILIMIT 0.140 to 0.210A at 150oC
• Built in Voltage Clamp
• Temperature Compensating PSPICE Model
• 2kV ESD Protected
• Controlled Switching Limits EMI and RFI
Packages
DRAIN
(FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
Description
The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE
are intelligent monolithic power circuits which incorporate a lat-
eral bipolar transistor, resistors, zener diodes and a power MOS
transistor. The current limiting of these devices allow it to be used
safely in circuits where a shorted load condition may be encoun-
tered. The drain-source voltage clamping offers precision control
of the circuit voltage when switching inductive loads. The “Logic
Level” gate allows this device to be fully biased on with only 5.0V
from gate to source, thereby facilitating true on-off power control
directly from logic level (5V) integrated circuits.
DRAIN
(FLANGE)
JEDEC TO-251AA
SOURCE
DRAIN
GATE
JEDEC TO-252AA
GATE
SOURCE
DRAIN
(FLANGE)
The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE
incorporate ESD protection and are designed to withstand 2kV
(Human Body Model) of ESD.
PACKAGING AVAILABILITY
Symbol
D
PART NUMBER
PACKAGE
BRAND
RLD03N06CLE
TO-251AA
03N06C
RLD03N06CLESM TO-252AA
03N06C
RLP03N06CLE
TO-220AB
03N06CLE
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e.
RLD03N06CLESM9A.
Formerly developmental type TA49026.
G
S
Absolute Maximum Ratings TC = +25oC
Drain Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS
Drain Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate Source Voltage (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Reverse Voltage Gate Bias Not Allowed
Drain Current
RMS Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Power Dissipation
TC = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate above +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PT
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . . . . . . . . ESD
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSTG, TJ
RLD03N06CLE,
RLD03N06CLESM,
RLP03N06CLE
60
60
+5.5
Self Limited
30
0.2
2
-55 to +175
UNITS
V
V
V
W
W/oC
KV
oC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures.
Copyright © Harris Corporation 1996
1
File Number 3948.3
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RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Test Circuit and Waveform
VDD
RL
VDS
VDS
tON
tD(ON)
tR
90%
tOFF
tD(OFF)
tF
90%
VGS
0V
RGS
DUT
10%
VGS
10%
50%
PULSE WIDTH
10%
90%
50%
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
Detailed Description
Temperature Dependence of Current Limiting and
Switching Speed Performance
The RLD03N06CLE, RLD03N06CLESM and RLP03N06CLE
are a monolithic power device which incorporates a Logic Level
power MOSFET transistor with a current sensing scheme and
control circuitry to enable the device to self limit the drain
source current flow. The current sensing scheme supplies cur-
rent to a resistor that is connected across the base to emitter of
a bipolar transistor in the control section. The collector of this
bipolar transistor is connected to the gate of the power MOS-
FET transistor. When the ratiometric current from the current
sensing reaches the value required to forward bias the base
emitter junction of this bipolar transistor, the bipolar “turns on”.
A resistor is incorporated in series with the gate of the power
MOSFET transistor allowing the bipolar transistor to adjust the
drive on the gate of the power MOSFET transistor to a voltage
which then maintains a constant current in the power MOSFET
transistor. Since both the ratiometric current sensing scheme
and the base emitter unction voltage of the bipolar transistor
vary with temperature, the current at which the device limits is a
function of temperature. This dependence is shown in Figure 3.
The resistor in series with the gate of the power MOSFET
transistor also results in much slower switching performance
than in standard power MOSFET transistors. This is an
advantage where fast switching can cause EMI or RFI. The
switching speed is very predictable.
DC Operation
The limit on the drain to source voltage for operation in cur-
rent limiting on a steady state (DC) basis is shown in the
equation below. The dissipation in the device is simply the
applied drain to source voltage multiplied by the limiting cur-
rent. This device, like most power MOSFET devices today, is
limited to 175oC. The maximum voltage allowable can,
therefore, be expressed as shown in Equation 1:
VDS = (--I-1-L--5--M--0---•°---C-(--R--–--θ-T--J-A--C---M--+---B-R--I--Eθ---J-N--A--T--)--)-
(EQ. 1)
The results of this equation are plotted in Figure 15 for vari-
ous heatsinks.
Duty Cycle Operation
In many applications either the drain to source voltage or the
gate drive is not available 100% of the time. The copper
header on which the RLD03N06CLE, RLD03N06CLESM
and RLP03N06CLE is mounted has a very large thermal
storage capability, so for pulse widths of less then 1ms, the
temperature of the header can be considered a constant,
thereby the junction temperature can be calculated simply as
shown in Equation 2:
TC = (VDS • ID • D • RθCA) + TA MBIENT
(EQ. 2)
Generally the heat storage capability of the silicon chip in a
power transistor is ignored for duty cycle calculations. Mak-
ing this assumption, limiting junction temperature to 175oC
and using the TC calculated in Equation 2, the expression for
maximum VDS under duty cycle operation is shown in Equa-
tion 3:
VDS = I--L----1M---5---0-•---o-D--C----•--–--R---T-θ---C-J---C---
(EQ. 3)
These values are plotted as Figures 16 through 21 for vari-
ous heatsink thermal resistances.
Limited Time Operations
Protection for a limited period of time is sufficient for many
applications. As stated above the heat storage in the silicon
chip can usually be ignored for computations of over 10 ms,
thereby the thermal equivalent circuit reduces to a simple
enough circuit to allow easy computation on the limiting con-
ditions. The variation in limiting current with temperature
complicates the calculation of junction temperature, but a
simple straight line approximation of the variation is accurate
enough to allow meaningful computations. The curves
shown as Figures 22 through 25 (RLP03N06CLE) and Fig-
ure 26 through 29 (RLD03N06CLE and RLD03N06CLESM)
give an accurate indication of how long the specified voltage
can be applied to the device in the current limiting mode
without exceeding the maximum specified 175oC junction
temperature. In practice this tells you how long you have to
alleviate the condition causing the current limiting to occur.
5
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| Part Number | Description | MFRS |
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